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[209.132.180.67]) by mx.google.com with ESMTP id g14si22781321pgh.98.2019.07.17.00.02.48; Wed, 17 Jul 2019 00:03:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726055AbfGQHCP (ORCPT + 99 others); Wed, 17 Jul 2019 03:02:15 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:46470 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725873AbfGQHCP (ORCPT ); Wed, 17 Jul 2019 03:02:15 -0400 X-UUID: 178f1f2683724f59a40625aed9c447b8-20190717 X-UUID: 178f1f2683724f59a40625aed9c447b8-20190717 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1071939593; Wed, 17 Jul 2019 15:01:50 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 17 Jul 2019 15:01:48 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 17 Jul 2019 15:01:48 +0800 Message-ID: <1563346908.29169.28.camel@mtksdaap41> Subject: Re: [PATCH v4, 25/33] drm/mediatek: add clock property check before get it From: CK Hu To: CC: Philipp Zabel , Rob Herring , Matthias Brugger , "David Airlie" , Daniel Vetter , Mark Rutland , , , , , Date: Wed, 17 Jul 2019 15:01:48 +0800 In-Reply-To: <1562625253-29254-26-git-send-email-yongqiang.niu@mediatek.com> References: <1562625253-29254-1-git-send-email-yongqiang.niu@mediatek.com> <1562625253-29254-26-git-send-email-yongqiang.niu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-SNTS-SMTP: DBE8AFB5AD53D33AE2D0AB8EF4693F5CD67E9E7F3DEEF7454E41BD6BB0BDA92E2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Yongqiang: On Tue, 2019-07-09 at 06:34 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu > > This patch add clock property check before get it > > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index c57e7ab..a9d3e27 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -668,10 +668,12 @@ static int mtk_ddp_probe(struct platform_device *pdev) > for (i = 0; i < 10; i++) > ddp->mutex[i].id = i; > > - ddp->clk = devm_clk_get(dev, NULL); > - if (IS_ERR(ddp->clk)) { > - dev_err(dev, "Failed to get clock\n"); > - return PTR_ERR(ddp->clk); > + if (of_find_property(dev->of_node, "clocks", &i)) { > + ddp->clk = devm_clk_get(dev, NULL); > + if (IS_ERR(ddp->clk)) { > + dev_err(dev, "Failed to get clock\n"); > + return PTR_ERR(ddp->clk); > + } Only "mediatek,mt8133-disp-mutex" has no clock property. For other SoC, clock property is required. So I think this exception is just for mt8183. Regards, CK > } > > regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);