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From:   Krzysztof Kozlowski <krzk@kernel.org>
Date:   Wed, 17 Jul 2019 10:48:10 +0200
Message-ID: <CAJKOXPd0kzwZ9_eCK9r04Qj0Rf5SSSnMmwDj11cZozmu0gqsgw@mail.gmail.com>
Subject: Re: [PATCH v1 21/50] ARM: dts: exynos: add OPP into FSYS APB bus in Exynos5420
To:     Lukasz Luba <l.luba@partner.samsung.com>
Cc:     devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org,
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On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> Add an OPP for FSYS APB which reflects the real possible frequency.
> The bus will have a new parent clock which speed has 600MHz, thus
> a new possible frequency provided by the clock divider is 150MHz.
> According to the documentation max possible frequency for this bus is
> 200MHz.

Commit msg is good but title could be improved. Focus in the title
what problem/issue you are solving - add intermediate step in scaling
of FSYS APB?

Best regards,
Krzysztof