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Wed, 17 Jul 2019 10:29:50 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20190717102950eusmtrp2ab26d6fd408c395bc65ce131d4b75e62~yKxUYVHOR2136421364eusmtrp2B; Wed, 17 Jul 2019 10:29:50 +0000 (GMT) X-AuditID: cbfec7f2-f13ff700000010ca-a7-5d2ef89e2b48 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id B1.73.04140.E98FE2D5; Wed, 17 Jul 2019 11:29:50 +0100 (BST) Received: from [106.120.51.20] (unknown [106.120.51.20]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20190717102949eusmtip2b83dba6b3f3830bea72db3b9ad1feb3a~yKxTqqxIs1285512855eusmtip2_; Wed, 17 Jul 2019 10:29:49 +0000 (GMT) Subject: Re: [PATCH v1 27/50] ARM: dts: exynos: align bus_wcore OPPs in Exynos5420 To: Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "linux-samsung-soc@vger.kernel.org" , linux-clk@vger.kernel.org, mturquette@baylibre.com, sboyd@kernel.org, =?UTF-8?Q?Bart=c5=82omiej_=c5=bbo=c5=82nierkiewicz?= , kgene@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, Chanwoo Choi , kyungmin.park@samsung.com, Andrzej Hajda , Marek Szyprowski , s.nawrocki@samsung.com, myungjoo.ham@samsung.com From: Lukasz Luba Message-ID: <701cbb66-17cb-9f32-1da4-4129a787fc7f@partner.samsung.com> Date: Wed, 17 Jul 2019 12:29:48 +0200 User-Agent: Mozilla/5.0 (X11; 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charset="utf-8" X-RootMTR: 20190715124456eucas1p2acf15d00e3fa7b77fe3a2b10ce1ab74f X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190715124456eucas1p2acf15d00e3fa7b77fe3a2b10ce1ab74f References: <20190715124417.4787-1-l.luba@partner.samsung.com> <20190715124417.4787-28-l.luba@partner.samsung.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 7/17/19 12:15 PM, Krzysztof Kozlowski wrote: > On Mon, 15 Jul 2019 at 14:44, Lukasz Luba wrote: >> >> This is the most important bus in the Exynos5x SoC. The whole communication >> inside SoC does through that bus (apart from direct requests from CCI to >> DRAM controller). It is also modeled as a master bus in devfreq framework. >> It is also the only one OPP table throughout other buses which has voltage >> values. The devfreq software controls the speed of that bus and other >> buses. The other buses follows the rate of the master. There is only one >> regulator. The old lowest OPP had pair 925mV, 84MHz which is enough for > > s/lowest/slowest/ OK > >> this frequency. However, due to the fact that the other buses follows the >> WCORE bus by taking the OPP from their table with the same id, e.g. opp02, >> the children frequency should be stable with the set voltage. >> It could cause random faults very hard to debug. >> Thus, the patch removes the lowest OPP to make other buses' lowest OPPs > > s/lowest/slowest/ OK > >> working. The new lowest OPP has voltage high enough for buses working up >> to 333MHz. It also changes the frequencies of the OPPs to align them to >> PLL value such that it is possible to set them using only a divider without >> reprogramming OPP. > > Reprogramming OPP? What is it? Mistake, should be PLL. Thanks for that. > >> Reprogramming the PLL was not set, so the real frequency > > I understood from the previous that reprogramming the OPP (PLL?) was > happening... Please rephrase entire sentence. Yes, I will rewrite it when I will combine these patches into one. Regards, Lukasz > > BR, > Krzysztof > >> values were not the one from the OPP table, which could confuse the >> governor algorithms which relay on OPP speed values making the system to >> behave weird. >> >> Signed-off-by: Lukasz Luba >> --- >> arch/arm/boot/dts/exynos5420.dtsi | 12 ++++-------- >> 1 file changed, 4 insertions(+), 8 deletions(-) >> >> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi >> index f8c36ff0d4c3..a355c76af5a5 100644 >> --- a/arch/arm/boot/dts/exynos5420.dtsi >> +++ b/arch/arm/boot/dts/exynos5420.dtsi >> @@ -1107,22 +1107,18 @@ >> compatible = "operating-points-v2"; >> >> opp00 { >> - opp-hz = /bits/ 64 <84000000>; >> - opp-microvolt = <925000>; >> + opp-hz = /bits/ 64 <150000000>; >> + opp-microvolt = <950000>; >> }; >> opp01 { >> - opp-hz = /bits/ 64 <111000000>; >> + opp-hz = /bits/ 64 <200000000>; >> opp-microvolt = <950000>; >> }; >> opp02 { >> - opp-hz = /bits/ 64 <222000000>; >> + opp-hz = /bits/ 64 <300000000>; >> opp-microvolt = <950000>; >> }; >> opp03 { >> - opp-hz = /bits/ 64 <333000000>; >> - opp-microvolt = <950000>; >> - }; >> - opp04 { >> opp-hz = /bits/ 64 <400000000>; >> opp-microvolt = <987500>; >> }; >> -- >> 2.17.1 >> > >