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Wed, 17 Jul 2019 15:58:10 +0000 From: Paul Burton To: Vladimir Kondratiev CC: Ralf Baechle , Paul Burton , James Hogan , "linux-mips@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Vladimir Kondratiev , "linux-mips@vger.kernel.org" Subject: Re: [PATCH] mips: fix cacheinfo Thread-Topic: [PATCH] mips: fix cacheinfo Thread-Index: AQHVO6lDkTC8sdb3XkmqC6T/u/Yn+6bO+YiA Date: Wed, 17 Jul 2019 15:58:10 +0000 Message-ID: References: <20190716073656.24924-1-vladimir.kondratiev@linux.intel.com> In-Reply-To: <20190716073656.24924-1-vladimir.kondratiev@linux.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR07CA0048.namprd07.prod.outlook.com (2603:10b6:a03:60::25) To MWHPR2201MB1277.namprd22.prod.outlook.com (2603:10b6:301:18::12) authentication-results: spf=none (sender IP is ) smtp.mailfrom=pburton@wavecomp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [12.94.197.246] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: e87c0d94-3f1e-4864-9c4e-08d70acf910c x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(2017052603328)(7193020);SRVR:MWHPR2201MB1182; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: mips.com X-MS-Exchange-CrossTenant-Network-Message-Id: e87c0d94-3f1e-4864-9c4e-08d70acf910c X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jul 2019 15:58:10.5696 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: pburton@wavecomp.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR2201MB1182 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello, Vladimir Kondratiev wrote: > Because CONFIG_OF defined for MIPS, cacheinfo attempts to fill informatio= n > from DT, ignoring data filled by architecture routine. This leads to erro= r > reported >=20 > cacheinfo: Unable to detect cache hierarchy for CPU 0 >=20 > Way to fix this provided in > commit fac51482577d ("drivers: base: cacheinfo: fix x86 with > CONFIG_OF enabled") >=20 > Utilize same mechanism to report that cacheinfo set by architecture > specific function >=20 > Signed-off-by: Vladimir Kondratiev Applied to mips-fixes. Thanks, Paul [ This message was auto-generated; if you believe anything is incorrect then please email paul.burton@mips.com to report it. ]