Received: by 2002:a25:ad19:0:0:0:0:0 with SMTP id y25csp2010533ybi; Thu, 18 Jul 2019 01:59:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqw3mcH2rzvd64QJ92nY2ZyiBWMkkNLb+g2KV9S2RCKna9CsKrUBxRJOE3BxpVLUoKFG9wqN X-Received: by 2002:a17:90a:6546:: with SMTP id f6mr4039549pjs.11.1563440377550; Thu, 18 Jul 2019 01:59:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1563440377; cv=none; d=google.com; s=arc-20160816; b=tpJ3SiF1w9UNu9yJ2j9XKkf+Kjr+Vobz1Q9k/PXPJFh+Fnf1JAdIv1gMr70Y+231CC W6Luqi+BZPrQWlshAydVkIg3caX13rslX9c3T6Gx03qySJVboXm915GG0JH3577vlY/z HNrmrOYIJbEn0C8TC21zuR/8UEn8PEPPnBfMIkW/xSyTw4zMf+8pyBi5Ym6RkPunxzHv 1lKC8qtbMGH+DvHzirSUiFsqnYFMvNbGvnk2QSZEFN+WIT9sh/znHeaJV5UqPTo+aEcK Wh7DYJxjCsOMo2LrrKwJFy9WWQFD3iLGeYmkjAWgQQQ0mDIuvSTZOWoD+F5tXVL/Funy RS+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:references :in-reply-to:subject:cc:to:from; bh=5SBMtbiubPaA9yGE80bn3V3EuPNJAzzdGi+CPdeI32Q=; b=Zix7QJ5YotelaHamNBsvWk1Zhhk3DtDiho1U0M7lcC3Xgf6t11NEPW4byWVPwXH9tn 5SoHpCZWddqAlTNr5ZPnqoLtSp2DeyRfwqXwjwntU39r/aW7G/OsbBup/dawUEf2BL8r 3F+EP812RmmmS5LpnxWGikaANFBn8PKVdPWWTjl+jM1TUpeX8P0xKWFpdVIGWX/Guys7 1+TRbVGZxlI0N/FzgaluoCRLfEV4ziGixA4N89lzSA6y7owQzw7jiiBgC84eYJLdYY3z OnAtcuh3qFqpGs6mANGkuA+hTpIg2lUZ545YXRmf19S7XXBzKKocrPobETtpXd4Bwigc W74w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j74si1331332pje.12.2019.07.18.01.59.20; Thu, 18 Jul 2019 01:59:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389500AbfGRI6O (ORCPT + 99 others); Thu, 18 Jul 2019 04:58:14 -0400 Received: from mga17.intel.com ([192.55.52.151]:10418 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726383AbfGRI6N (ORCPT ); Thu, 18 Jul 2019 04:58:13 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Jul 2019 01:58:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,276,1559545200"; d="scan'208";a="173124356" Received: from pipin.fi.intel.com (HELO pipin) ([10.237.72.175]) by orsmga006.jf.intel.com with ESMTP; 18 Jul 2019 01:58:10 -0700 From: Felipe Balbi To: Richard Cochran Cc: netdev@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H . Peter Anvin" , x86@kernel.org, linux-kernel@vger.kernel.org, "Christopher S . Hall" Subject: Re: [RFC PATCH 0/5] PTP: add support for Intel's TGPIO controller In-Reply-To: <20190717173915.GE1464@localhost> References: <20190716072038.8408-1-felipe.balbi@linux.intel.com> <20190716164123.GB2125@localhost> <87ef2p2lvc.fsf@linux.intel.com> <20190717173915.GE1464@localhost> Date: Thu, 18 Jul 2019 11:58:09 +0300 Message-ID: <87imrziuse.fsf@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Richard Cochran writes: > On Wed, Jul 17, 2019 at 09:52:55AM +0300, Felipe Balbi wrote: >> >> It's just a pin, like a GPIO. So it would be a PCB trace, flat flex, >> copper wire... Anything, really. > > Cool. Are there any Intel CPUs available that have this feature? At least canon lake has it, but its BIOS doesn't enable it. This is something that will be more important on future CPUs. -- balbi