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[209.132.180.67]) by mx.google.com with ESMTP id d10si1038265pgl.163.2019.07.18.23.35.23; Thu, 18 Jul 2019 23:35:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=QSOwOufE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726709AbfGSGet (ORCPT + 99 others); Fri, 19 Jul 2019 02:34:49 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:35060 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726067AbfGSGes (ORCPT ); Fri, 19 Jul 2019 02:34:48 -0400 Received: by mail-wr1-f67.google.com with SMTP id y4so31062318wrm.2; Thu, 18 Jul 2019 23:34:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=kMcKTsEVyji+n2fYLtlne8FEnWZcMA2/ktkd0SxT+VI=; b=QSOwOufE4zhKaOthPkDk7gWdX3qwYegZikq56s0mkeTwW5vSbnTSAff0lcnACu34zb vdRjrjSoxzugWQ5xieksmi9CByUQ5AnlvJvPceiVK6Sma4J2CcItR6GSqE/+xv2rjim9 hszdEfhJIQs0Cvwusfs52LSo1AccmTUPJozjSty8KUF6cjhaQHqgQxUAgI0dd8a4xTnH BZ8cKAEWJkxNC2IOVZ6nJ+kTlghlY5buBFzyqooQ2Jiy3cOwUPAYOLNzB/9wFrTNfb72 p9dkMyMTd4O6yToPz/j1GJ9UScDq+CL+Hi80pQVbp5CH5uBdZp0mNnDg/VSEYBXXVgOE ehYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=kMcKTsEVyji+n2fYLtlne8FEnWZcMA2/ktkd0SxT+VI=; b=BILJIDFTiLJd6KQpuJOQE9102mtBhs0Gesstd355vEv53pVH5YpninYpuzepLU6/IK 5qx9irZVuyVpmP6sP65zYReupDmBrFUjWdeG8Sf7qSDk6poCR4pUBrtRC618QuWrnY9Y 9FdAkTAliSbif+WcdO38zFv/SzRv9r6Wn+f5dH1SHSg87UzteIi+PSgMqemtVNRbhqq3 YP4+L+qOsSaXNKcVgq/mj0oX6pYHnK1oYWPWkBfTLPRIepIoKlbhY2qBxtuFeT0QgUtq JS8OPQ92ASJfRMRWhf3o35X2F/dCZzoHLQnVKXOHHHZyvYZiF6l+JeXE9GVu/MSXnHZ5 Nx1Q== X-Gm-Message-State: APjAAAUTuxFSwkXPusqmSGYuT4NSCRlEa+4gaKO9tspXTaUbOnR7biK8 lTq5yylCqjo3tcrihqOS+HpQsdYAjL/auJCOiB4= X-Received: by 2002:a05:6000:14b:: with SMTP id r11mr54574650wrx.196.1563518086309; Thu, 18 Jul 2019 23:34:46 -0700 (PDT) MIME-Version: 1.0 References: <20190718151346.3523-1-daniel.baluta@nxp.com> <20190718151346.3523-4-daniel.baluta@nxp.com> In-Reply-To: From: Daniel Baluta Date: Fri, 19 Jul 2019 09:34:34 +0300 Message-ID: Subject: Re: [PATCH 3/3] dt-bindings: dsp: fsl: Add DSP core binding support To: Leonard Crestez Cc: Rob Herring , Daniel Baluta , Shawn Guo , Mark Rutland , Sascha Hauer , Sascha Hauer , Fabio Estevam , dl-linux-imx , "S.j. Wang" , Paul Olaru , Aisheng Dong , Anson Huang , Peng Fan , Frank Li , Devicetree List , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , "linux-kernel@vger.kernel.org" , "sound-open-firmware@alsa-project.org" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jul 18, 2019 at 9:40 PM Leonard Crestez wrote: > > On 18.07.2019 21:24, Daniel Baluta wrote: > > On Thu, Jul 18, 2019 at 7:41 PM Rob Herring wrote: > >> > >> On Thu, Jul 18, 2019 at 9:13 AM Daniel Baluta wrote: > >>> > >>> This describes the DSP device tree node. > >>> > >>> Signed-off-by: Daniel Baluta > > >>> + power-domains: > >>> + description: > >>> + List of phandle and PM domain specifier as documented in > >>> + Documentation/devicetree/bindings/power/power_domain.txt > >> > >> How many? 4? > > > > Yes, 4 for i.MX8QXP. Also, the same number is for i.MX8QM. Anyhow, I didn't > > added added a limit here because I really don't know how many will be > > in upcoming i.MX platforms. > > Which 4? It might help to use power-domain-names explicitly just like > it's done for clocks and mboxes. > > This is very common for phandle lists. 4 like in the example at the bottom of the patch: + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>; Not sure if it makes sense to use power-domain-names as the driver parses directly the "power-domains" property.