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From:   Gustavo Pimentel <Gustavo.Pimentel@synopsys.com>
To:     Jonathan Chocron <jonnyc@amazon.com>,
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Subject: RE: [PATCH v2 7/8] PCI: dw: Add validation that PCIe core is set to
 correct mode
Thread-Topic: [PATCH v2 7/8] PCI: dw: Add validation that PCIe core is set to
 correct mode
Thread-Index: AQHVPU4E178VJy6TjkK4KITScO7kRKbRqjIw
Date:   Fri, 19 Jul 2019 09:15:16 +0000
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References: <20190718094531.21423-1-jonnyc@amazon.com>
 <20190718094718.25083-3-jonnyc@amazon.com>
In-Reply-To: <20190718094718.25083-3-jonnyc@amazon.com>
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On Thu, Jul 18, 2019 at 10:47:17, Jonathan Chocron <jonnyc@amazon.com>=20
wrote:

> Some PCIe controllers can be set to either Host or EP according to some
> early boot FW. To make sure there is no discrepancy (e.g. FW configured
> the port to EP mode while the DT specifies it as a host bridge or vice
> versa), a check has been added for each mode.
>=20
> Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
> ---
>  drivers/pci/controller/dwc/pcie-designware-ep.c   | 8 ++++++++
>  drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++
>  2 files changed, 16 insertions(+)
>=20
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pc=
i/controller/dwc/pcie-designware-ep.c
> index 2bf5a35c0570..00e59a134b93 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -531,6 +531,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
>  	int ret;
>  	u32 reg;
>  	void *addr;
> +	u8 hdr_type;
>  	unsigned int nbars;
>  	unsigned int offset;
>  	struct pci_epc *epc;
> @@ -543,6 +544,13 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
>  		return -EINVAL;
>  	}
> =20
> +	hdr_type =3D dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
> +	if (hdr_type !=3D PCI_HEADER_TYPE_NORMAL) {
> +		dev_err(pci->dev, "PCIe controller is not set to EP mode (hdr_type:0x%=
x)!\n",
> +			hdr_type);
> +		return -EIO;
> +	}
> +
>  	ret =3D of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows)=
;
>  	if (ret < 0) {
>  		dev_err(dev, "Unable to read *num-ib-windows* property\n");
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/=
pci/controller/dwc/pcie-designware-host.c
> index f93252d0da5b..d2ca748e4c85 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -323,6 +323,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
>  	struct pci_bus *child;
>  	struct pci_host_bridge *bridge;
>  	struct resource *cfg_res;
> +	u8 hdr_type;
>  	int ret;
> =20
>  	raw_spin_lock_init(&pci->pp.lock);
> @@ -396,6 +397,13 @@ int dw_pcie_host_init(struct pcie_port *pp)
>  		}
>  	}
> =20
> +	hdr_type =3D dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
> +	if (hdr_type !=3D PCI_HEADER_TYPE_BRIDGE) {
> +		dev_err(pci->dev, "PCIe controller is not set to bridge type (hdr_type=
: 0x%x)!\n",
> +			hdr_type);
> +		return -EIO;
> +	}
> +
>  	pp->mem_base =3D pp->mem->start;
> =20
>  	if (!pp->va_cfg0_base) {
> --=20
> 2.17.1

It doesn't harm.
Thanks.

Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>