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<07897688-2a02-b7a7-7048-72c4078d26a2@gmail.com> <90e1a90b-1d33-a5db-9af8-dc5c5d45b65f@nvidia.com> From: Sowjanya Komatineni Message-ID: Date: Mon, 22 Jul 2019 00:36:27 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.2 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: quoted-printable Content-Language: en-US DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563780969; bh=02bX3AGiinZxnBdCIPZ8N6iwcluRP9G7/KgP0IdvRtQ=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Transfer-Encoding: Content-Language; b=rLnZFugFpTTFefufYlAW57j01UR16eHnrXkKOM1GMll6qiNMivX2+LpxUHwiLrhOb njFLm7+UEslBviZwsWE/CvdEcaIYaLfbG1+8rgyUwzi1jlYX6N/PSdQAru0hQGhsA2 fTRg+g9I9MKU3N+ZKX9sVeX0TaXL2FIo/iic+zTY92dyFlu27S6FBmYvV8vQ86fjEE FOGjgle5HKwCKPDmusonPgxh5Wp0op4aZ2Lv84zlSsf/lGjB2shhR6SolAqZ3pWixx qZJU3Ur2k24CgPo8mquogEecJMvDUR2A7Rs+L7HzgTox3qkgkYaovfdJvZHeTfS5aA 8f8tCivgfcyWQ== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 7/22/19 12:30 AM, Dmitry Osipenko wrote: > 22.07.2019 10:24, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >> On 7/22/19 12:17 AM, Dmitry Osipenko wrote: >>> 22.07.2019 10:12, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >>>> On 7/21/19 11:32 PM, Dmitry Osipenko wrote: >>>>> 22.07.2019 6:17, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >>>>>> On 7/21/19 3:39 PM, Sowjanya Komatineni wrote: >>>>>>> On 7/21/19 2:16 PM, Dmitry Osipenko wrote: >>>>>>>> 21.07.2019 22:40, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1= =82: >>>>>>>>> This patch has a fix to enable PLLP branches to CPU before changi= ng >>>>>>>>> the CPU clusters clock source to PLLP for Gen5 Super clock. >>>>>>>>> >>>>>>>>> During system suspend entry and exit, CPU source will be switched >>>>>>>>> to PLLP and this needs PLLP branches to be enabled to CPU prior t= o >>>>>>>>> the switch. >>>>>>>>> >>>>>>>>> On system resume, warmboot code enables PLLP branches to CPU and >>>>>>>>> powers up the CPU with PLLP clock source. >>>>>>>>> >>>>>>>>> Signed-off-by: Sowjanya Komatineni >>>>>>>>> --- >>>>>>>>> =C2=A0=C2=A0=C2=A0 drivers/clk/tegra/clk-super.c=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 11 +++++++++++ >>>>>>>>> =C2=A0=C2=A0=C2=A0 drivers/clk/tegra/clk-tegra-super-gen4.c |=C2= =A0 4 ++-- >>>>>>>>> =C2=A0=C2=A0=C2=A0 drivers/clk/tegra/clk.h=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 |=C2=A0 4 ++++ >>>>>>>>> =C2=A0=C2=A0=C2=A0 3 files changed, 17 insertions(+), 2 deletion= s(-) >>>>>>>>> >>>>>>>>> diff --git a/drivers/clk/tegra/clk-super.c >>>>>>>>> b/drivers/clk/tegra/clk-super.c >>>>>>>>> index 39ef31b46df5..d73c587e4853 100644 >>>>>>>>> --- a/drivers/clk/tegra/clk-super.c >>>>>>>>> +++ b/drivers/clk/tegra/clk-super.c >>>>>>>>> @@ -28,6 +28,9 @@ >>>>>>>>> =C2=A0=C2=A0=C2=A0 #define super_state_to_src_shift(m, s) ((m->w= idth * s)) >>>>>>>>> =C2=A0=C2=A0=C2=A0 #define super_state_to_src_mask(m) (((1 << m-= >width) - 1)) >>>>>>>>> =C2=A0=C2=A0=C2=A0 +#define CCLK_SRC_PLLP_OUT0 4 >>>>>>>>> +#define CCLK_SRC_PLLP_OUT4 5 >>>>>>>>> + >>>>>>>>> =C2=A0=C2=A0=C2=A0 static u8 clk_super_get_parent(struct clk_hw = *hw) >>>>>>>>> =C2=A0=C2=A0=C2=A0 { >>>>>>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 struct tegra_clk_supe= r_mux *mux =3D to_clk_super_mux(hw); >>>>>>>>> @@ -97,6 +100,14 @@ static int clk_super_set_parent(struct clk_hw >>>>>>>>> *hw, u8 index) >>>>>>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 if (index =3D=3D mux->div2_index) >>>>>>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 index =3D mux->pllx_index; >>>>>>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } >>>>>>>>> + >>>>>>>>> +=C2=A0=C2=A0=C2=A0 /* >>>>>>>>> +=C2=A0=C2=A0=C2=A0=C2=A0 * Enable PLLP branches to CPU before se= lecting PLLP source >>>>>>>>> +=C2=A0=C2=A0=C2=A0=C2=A0 */ >>>>>>>>> +=C2=A0=C2=A0=C2=A0 if ((mux->flags & TEGRA_CPU_CLK) && >>>>>>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ((index =3D=3D CCLK_S= RC_PLLP_OUT0) || (index =3D=3D >>>>>>>>> CCLK_SRC_PLLP_OUT4))) >>>>>>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 tegra_clk_set_pllp_ou= t_cpu(true); >>>>>>>> Should somewhere here be tegra_clk_set_pllp_out_cpu(false) when >>>>>>>> switching from PLLP? >>>>>>> PLLP may be used for other CPU clusters. >>>>>> Though to avoid flag and check needed to make sure other CPU is not >>>>>> using before disabling PLLP branch to CPU. >>>>>> >>>>>> But leaving it enabled shouldn't impact much as clock source mux is >>>>>> after this in design anyway. >>>>>> >>>>>> But can add as well if its clear that way. >>>>> The TRM doc says "The CPU subsystem supports a switch-cluster mode >>>>> meaning that only one of the clusters can be active at any given time= ". >>>>> >>>>> Given that cluster-switching isn't supported in upstream, I don't thi= nk >>>>> that you need to care about the other cluster at all, at least for no= w. >>>>> >>>>> The cluster-switching implementation in upstream is very complicated >>>>> because it requires a special "hotplugging" CPU governor, which >>>>> apparently no other platform needs. >>>>> >>>>> [snip] >>>> This patch enables PLLP branches to CPU for both CPUG & CPULP if they >>>> use PLLP source. >>>> >>>> So, to disable PLLP out CPU when not in use, we still need check for >>>> other cluster because during resume both LP CPU and G CPU gets restore= d. >>>> CPUG runs from PLLP on resume and when it does super clk restore for L= P >>>> CPU which may not be using PLLP, but as both uses same super mux >>>> clk_ops, without check (for PLLP branch to CPU in use) disabling PLLP >>>> branch to CPU during LP CPU restore looses clock to CPU G as well whic= h >>>> is running from PLLP. >>>> >>>> Will add check and disable PLLP if not in use in next version... this >>>> need extern flag as well to mark PLLP usage with either of CPU's. >>> I still don't understand why do you need to care about LP cluster at >>> all, given that it's always in a power-gated state. >> cclk_lp is registered thru super clk mux which uses same clk_ops as cclk= _g. >> >> during restore, cclk_lp also gets restored. So both cclk_lp & cclk_g >> goes thru same clk_ops >> >> In this patch, I marked super flags with TEGRA_CPU_CLK for both cclk_lp >> & cclk_g. >> >> So when cclk_lp restore happens, it goes thru same set_parent clk_ops >> and as its source is not PLLP, it tries to disable PLLP_OUT_CPU if its >> disabled without adding check for PLLP being in use by other cluster. > Ah, okay. > >> So either I should not mark cclk_lp as TEGRA_CPU_CLK and mark cclk_g >> only as TEGRA_CPU_CLK so PLLP out to CPU can be disabled without check >> if its not the source. >> >> OR >> >> With TEGRA_CPU_CLK used for both cclk_lp & cclk_g, need to add check if >> PLLP is in use so during cclk_lp restore it doesnt disable PLLP out to C= PU. >> >> >> To simplify without check, will just mark cclk_g super clock flag only >> as TEGRA_CPU_CLK so PLLP_OUT_CPU enable or disable happens only for CPUG > Sounds good. Then please add a brief comment to the CPULP, telling why > it misses the flag, for the record. Sure, will add comment.