Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
MIME-Version: 1.0
References: <20190722181945.244395-1-mka@chromium.org> <20190722202426.GL104440@art_vandelay>
In-Reply-To: <20190722202426.GL104440@art_vandelay>
From:   Doug Anderson <dianders@chromium.org>
Date:   Mon, 22 Jul 2019 13:57:14 -0700
Message-ID: <CAD=FV=Vk5V+gJhW8=6ZFfgV6LdN2U3-VkZvqn7QWDw-215-Z1Q@mail.gmail.com>
Subject: Re: [PATCH v2] drm/bridge: dw-hdmi: Refuse DDC/CI transfers on the
 internal I2C controller
To:     Sean Paul <sean@poorly.run>
Cc:     Matthias Kaehlcke <mka@chromium.org>,
        Andrzej Hajda <a.hajda@samsung.com>,
        Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
        David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>,
        dri-devel <dri-devel@lists.freedesktop.org>,
        LKML <linux-kernel@vger.kernel.org>,
        Jose Abreu <Jose.Abreu@synopsys.com>,
        Neil Armstrong <narmstrong@baylibre.com>,
        Adam Jackson <ajax@redhat.com>
Content-Type: text/plain; charset="UTF-8"
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

Hi,

On Mon, Jul 22, 2019 at 1:24 PM Sean Paul <sean@poorly.run> wrote:
>
> On Mon, Jul 22, 2019 at 11:19:45AM -0700, Matthias Kaehlcke wrote:
> > The DDC/CI protocol involves sending a multi-byte request to the
> > display via I2C, which is typically followed by a multi-byte
> > response. The internal I2C controller only allows single byte
> > reads/writes or reads of 8 sequential bytes, hence DDC/CI is not
> > supported when the internal I2C controller is used. The I2C
>
> This is very likely a stupid question, but I didn't see an answer for it, so
> I'll just ask :)
>
> If the controller supports xfers of 8 bytes and 1 bytes, could you just split
> up any of these transactions into len/8+len%8 transactions?

It's not quite that easy, I think.  Specifically a 1-byte transfer
isn't really a 1-byte transfer.

It always sticks this on the wire for a 1-byte write:

Start
Slave address (7 bits) + write (1 bit)
(wait ack)
Register address
1 byte of data
wait for ack
Stop

...or for a 1-byte read:

Start
Slave address (7 bits) + write (1 bit)
(wait ack)
Register address
(wait ack)
Repeated Start (1 bit)
Slave address (7 bits) + read (1 bit)
(read 1 byte of data)
Ack
Stop

Putting more than one of those in a row is not the same thing as just
doing a whole bunch of reads or a whole bunch of writes with no "stop"
in between.

As far as I could find out about DDC/CI it's part of the spec to _not_
send the stop between the reads / writes.


-Doug