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From:   Paul Burton <paul.burton@mips.com>
To:     Paul Cercueil <paul@crapouillou.net>
CC:     Ralf Baechle <ralf@linux-mips.org>,
        Paul Burton <pburton@wavecomp.com>,
        James Hogan <jhogan@kernel.org>, "od@zcrc.me" <od@zcrc.me>,
        "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Daniel Silsby <dansilsby@gmail.com>,
        Paul Cercueil <paul@crapouillou.net>,
        "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>
Subject: Re: [PATCH 2/5] MIPS: Add partial 32-bit huge page support
Thread-Topic: [PATCH 2/5] MIPS: Add partial 32-bit huge page support
Thread-Index: AQHVO1XoQ2GfGJeX6ka8ydBED/h9l6bXL9cA
Date:   Mon, 22 Jul 2019 21:20:17 +0000
Message-ID: <MWHPR2201MB127740D80392D2E38E0AB43CC1C40@MWHPR2201MB1277.namprd22.prod.outlook.com>
References: <20190715214003.9714-2-paul@crapouillou.net>
In-Reply-To: <20190715214003.9714-2-paul@crapouillou.net>
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Hello,

Paul Cercueil wrote:
> From: Daniel Silsby <dansilsby@gmail.com>
>=20
> This adds initial support for huge pages to 32-bit MIPS systems.
> Systems with extended addressing enabled (EVA,XPA,Alchemy/Netlogic)
> are not yet supported.
> With huge pages enabled, this implementation will increase page table
> memory overhead to match that of a 64-bit MIPS system. However, the
> cache-friendliness of page table walks is not affected significantly.
>=20
> Signed-off-by: Daniel Silsby <dansilsby@gmail.com>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>

Applied to mips-next.

Thanks,
    Paul

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