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From:   Paul Burton <paul.burton@mips.com>
To:     Paul Cercueil <paul@crapouillou.net>
CC:     Ralf Baechle <ralf@linux-mips.org>,
        James Hogan <jhogan@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>, "od@zcrc.me" <od@zcrc.me>,
        "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/2] MIPS: dts: ingenic: Add 'cpus' node
Thread-Topic: [PATCH 2/2] MIPS: dts: ingenic: Add 'cpus' node
Thread-Index: AQHVQLa+ICa8F+xhF0aMrnqoJdCEV6bXOEcA
Date:   Mon, 22 Jul 2019 22:28:59 +0000
Message-ID: <20190722222858.4nmhyzi45dg7u67u@pburton-laptop>
References: <20190722175548.18434-1-paul@crapouillou.net>
 <20190722175548.18434-2-paul@crapouillou.net>
In-Reply-To: <20190722175548.18434-2-paul@crapouillou.net>
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Hi Paul,

On Mon, Jul 22, 2019 at 01:55:48PM -0400, Paul Cercueil wrote:
> Add 'cpus' node to the jz4740.dtsi, jz4770.dtsi, jz4780.dtsi files.

What's the motivation for this?

If it's to silence the "cacheinfo: Unable to detect cache hierarchy"
messages, does commit b8bea8a5e5d9 ("mips: fix cacheinfo") from
mips-fixes work for you instead?

I'm not seeing much point listing cache setup in DT when we already
detect it from cop0 anyway.

Thanks,
    Paul

> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
>  arch/mips/boot/dts/ingenic/jz4740.dtsi | 19 +++++++++++
>  arch/mips/boot/dts/ingenic/jz4770.dtsi | 29 ++++++++++++++++
>  arch/mips/boot/dts/ingenic/jz4780.dtsi | 47 ++++++++++++++++++++++++++
>  3 files changed, 95 insertions(+)
>=20
> diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi b/arch/mips/boot/dts/=
ingenic/jz4740.dtsi
> index 2beb78a62b7d..14d777dae87d 100644
> --- a/arch/mips/boot/dts/ingenic/jz4740.dtsi
> +++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi
> @@ -6,6 +6,25 @@
>  	#size-cells =3D <1>;
>  	compatible =3D "ingenic,jz4740";
> =20
> +	cpus {
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type =3D "cpu";
> +			compatible =3D "ingenic,xburst-d0";
> +			reg =3D <0>;
> +			clocks =3D <&cgu JZ4740_CLK_CCLK>;
> +			clock-names =3D "cpu";
> +
> +			i-cache-size =3D <0x4000>;
> +			i-cache-block-size =3D <32>;
> +
> +			d-cache-size =3D <0x4000>;
> +			d-cache-block-size =3D <32>;
> +		};
> +	};
> +
>  	cpuintc: interrupt-controller {
>  		#address-cells =3D <0>;
>  		#interrupt-cells =3D <1>;
> diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi b/arch/mips/boot/dts/=
ingenic/jz4770.dtsi
> index 49ede6c14ff3..83ee526fbe10 100644
> --- a/arch/mips/boot/dts/ingenic/jz4770.dtsi
> +++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi
> @@ -7,6 +7,35 @@
>  	#size-cells =3D <1>;
>  	compatible =3D "ingenic,jz4770";
> =20
> +	cpus {
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type =3D "cpu";
> +			compatible =3D "ingenic,xburst-d1";
> +			reg =3D <0>;
> +			clocks =3D <&cgu JZ4770_CLK_CCLK>;
> +			clock-names =3D "cpu";
> +
> +			i-cache-size =3D <0x4000>;
> +			i-cache-block-size =3D <32>;
> +
> +			d-cache-size =3D <0x4000>;
> +			d-cache-block-size =3D <32>;
> +
> +			next-level-cache =3D <&L2_cache>;
> +
> +			L2_cache: cache-controller {
> +				compatible =3D "cache";
> +				cache-unified;
> +				cache-level =3D <2>;
> +				cache-size =3D <0x40000>;
> +				cache-block-size =3D <32>;
> +			};
> +		};
> +	};
> +
>  	cpuintc: interrupt-controller {
>  		#address-cells =3D <0>;
>  		#interrupt-cells =3D <1>;
> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/=
ingenic/jz4780.dtsi
> index b03cdec56de9..3339b37101c0 100644
> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> @@ -7,6 +7,53 @@
>  	#size-cells =3D <1>;
>  	compatible =3D "ingenic,jz4780";
> =20
> +	cpus {
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type =3D "cpu";
> +			compatible =3D "ingenic,xburst-e1";
> +			reg =3D <0>;
> +
> +			clocks =3D <&cgu JZ4780_CLK_CPU>;
> +			clock-names =3D "cpu";
> +
> +			i-cache-size =3D <0x8000>;
> +			i-cache-block-size =3D <32>;
> +
> +			d-cache-size =3D <0x8000>;
> +			d-cache-block-size =3D <32>;
> +
> +			next-level-cache =3D <&L2_cache>;
> +
> +			L2_cache: l2-cache {
> +				compatible =3D "cache";
> +				cache-unified;
> +				cache-level =3D <2>;
> +				cache-size =3D <0x80000>;
> +				cache-block-size =3D <32>;
> +			};
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type =3D "cpu";
> +			compatible =3D "ingenic,xburst-e1";
> +			reg =3D <1>;
> +
> +			clocks =3D <&cgu JZ4780_CLK_CORE1>;
> +			clock-names =3D "cpu";
> +
> +			i-cache-size =3D <0x8000>;
> +			i-cache-block-size =3D <32>;
> +
> +			d-cache-size =3D <0x8000>;
> +			d-cache-block-size =3D <32>;
> +
> +			next-level-cache =3D <&L2_cache>;
> +		};
> +	};
> +
>  	cpuintc: interrupt-controller {
>  		#address-cells =3D <0>;
>  		#interrupt-cells =3D <1>;
> --=20
> 2.21.0.593.g511ec345e18
>=20