Received: by 2002:a25:ad19:0:0:0:0:0 with SMTP id y25csp8702393ybi; Tue, 23 Jul 2019 13:27:36 -0700 (PDT) X-Google-Smtp-Source: APXvYqztz8lrHbCjn+4bYvLqZ+JUhBr8GFSJrUceOXmDLLO9T+vHmw3ZqeAkvgnk36rwfVwvU7nh X-Received: by 2002:a17:902:381:: with SMTP id d1mr80408414pld.331.1563913656727; Tue, 23 Jul 2019 13:27:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1563913656; cv=none; d=google.com; s=arc-20160816; b=dMGLZouQo+biEEcK1d3gD/RLE0gjMtMZakBiEh/23xwpXkLK8TeFAV8FAkcjVR2PcC +ShYbhqjhJj2iDW3YddC5vf7VPxUPwlvxTgE7y7pJFIbO3u5j6V0LNckRyhaCluBByVv bNtdmo0AxujXp6OclwZnxmqOOC2vXVfJT83pFEgkwrNWWZL30YkZQxdwiUCMBvDzclvW rFGTED+pN5ecO/K8s20zjvKrLVtqrneGsn37HiuxFVqOBNknNt9rN2UxPa7U8n74U+N5 Wc2FtsE+vI6S2OSv+yrucTQy4opZU1c0Dxlg/XeX4qtMKylrNmpyBfmC+Ega6Paj58S5 9s0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=iTNwazgo+YOd3iNY9H/41HeOTug8qaCt3eAOnjzFR6w=; b=nOa3AJt9rERZFRM54I526yCyTZjE/5wBW9AcrzU6jzGMCcSPLkVBccIYsqiiEYutN2 sup4YXWFoJtjnVyY9KDV7e/CB054SSMRKqyPKkCcqwHF23K1REI9n8T+TgkBePAPCRfu +0+Y+nuL6RO5Lc2SCvevW7Qj3psJwozwVYOR8nBiaqGqbvPoXeNgnhdNY0JpPxmNVrTN B5tP3dZ86+17wvAjQtEu6ceCnxDkKyOx5/SFRL3h3H5Xn4oWuuZfDpToyB5VT3ALoYrG yhQc01wB7vGS0zWEzScmtd2XoNvDkuDqgXIGYZFCCNwf6f43WBdxGLLP+l/YRCnbL7D/ cTYg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t191si11966225pgd.370.2019.07.23.13.27.20; Tue, 23 Jul 2019 13:27:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387883AbfGWKos (ORCPT + 99 others); Tue, 23 Jul 2019 06:44:48 -0400 Received: from foss.arm.com ([217.140.110.172]:52512 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726920AbfGWKor (ORCPT ); Tue, 23 Jul 2019 06:44:47 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2E51D337; Tue, 23 Jul 2019 03:44:47 -0700 (PDT) Received: from filthy-habits.cambridge.arm.com (filthy-habits.cambridge.arm.com [10.1.197.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 441A73F71A; Tue, 23 Jul 2019 03:44:46 -0700 (PDT) From: Marc Zyngier To: Thomas Gleixner , Jason Cooper , Julien Thierry , Rob Herring Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 0/9] irqchip/gic-v3: Add support for GICv3.1 extended PPI/SPI ranges Date: Tue, 23 Jul 2019 11:44:28 +0100 Message-Id: <20190723104437.154403-1-maz@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Apparently, having ~1000 wired interrupts is not enough, and some people need more. Fear not! The GIC Achitecture Department hereby grants you another 1024 SPIs, together with 64 PPIs, provided that you implement GICv3.1 (see [1] for the details) This series implements the required support, which requires a bit of infrastructure rework in order to make the thing less horrible... This has been tested on a FastModel. [1] https://developer.arm.com/docs/ihi0069/latest (version E) Marc Zyngier (9): irqchip/gic: Rework gic_configure_irq to take the full ICFGR base irqchip/gic-v3: Add INTID range and convertion primitives dt-bindings: interrupt-controller: arm,gic-v3: Describe ESPI range support irqchip/gic-v3: Add ESPI range support irqchip/gic: Prepare for more than 16 PPIs irqchip/gic-v3: Dynamically allocate PPI NMI refcounts irqchip/gic-v3: Dynamically allocate PPI partition descriptors dt-bindings: interrupt-controller: arm,gic-v3: Describe EPPI range support irqchip/gic-v3: Add EPPI range support .../interrupt-controller/arm,gic-v3.yaml | 6 +- drivers/irqchip/irq-gic-common.c | 33 +- drivers/irqchip/irq-gic-common.h | 2 +- drivers/irqchip/irq-gic-v3.c | 323 ++++++++++++++---- drivers/irqchip/irq-gic.c | 12 +- drivers/irqchip/irq-hip04.c | 9 +- include/linux/irqchip/arm-gic-v3.h | 29 +- 7 files changed, 319 insertions(+), 95 deletions(-) -- 2.20.1