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From:   Ulf Hansson <ulf.hansson@linaro.org>
Date:   Wed, 24 Jul 2019 09:19:30 +0200
Message-ID: <CAPDyKFqgTnudMumvrCJqi8FDfNNUU5AedP3hV=hwO1roG336Hw@mail.gmail.com>
Subject: Re: [PATCH 1/2] mmc: sdhci: Add PLL Enable support to internal clock setup
To:     Ben Chuang <ben.chuang@genesyslogic.com.tw>
Cc:     Adrian Hunter <adrian.hunter@intel.com>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        "linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>,
        johnsonm@danlj.org
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On Wed, 17 Jul 2019 at 04:39, Ben Chuang <ben.chuang@genesyslogic.com.tw> w=
rote:
>
> The GL9750 and GL9755 chipsets, and possibly others, require PLL Enable
> setup as part of the internal clock setup as described in 3.2.1 Internal
> Clock Setup Sequence of SD Host Controller Simplified Specification
> Version 4.20.  This changes the timeouts to the new specification of
> 150ms for each step and is documented as safe for "prior versions which
> do not support PLL Enable."
>
> Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
> Co-developed-by: Michael K Johnson <johnsonm@danlj.org>
> Signed-off-by: Michael K Johnson <johnsonm@danlj.org>
> ---
>  drivers/mmc/host/sdhci.c | 33 ++++++++++++++++++++++++---------
>  1 file changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 59acf8e3331e..fd684d7a5f15 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1636,15 +1636,11 @@ void sdhci_enable_clk(struct sdhci_host *host, u1=
6 clk)
>         clk |=3D SDHCI_CLOCK_INT_EN;
>         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
>
> -       /* Wait max 20 ms */
> -       timeout =3D ktime_add_ms(ktime_get(), 20);
> -       while (1) {
> -               bool timedout =3D ktime_after(ktime_get(), timeout);
> -
> -               clk =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL);
> -               if (clk & SDHCI_CLOCK_INT_STABLE)
> -                       break;
> -               if (timedout) {
> +       /* Wait max 150 ms */
> +       timeout =3D ktime_add_ms(ktime_get(), 150);
> +       while (!((clk =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL))
> +               & SDHCI_CLOCK_INT_STABLE)) {
> +               if (ktime_after(ktime_get(), timeout)) {
>                         pr_err("%s: Internal clock never stabilised.\n",
>                                mmc_hostname(host->mmc));
>                         sdhci_dumpregs(host);
> @@ -1653,8 +1649,27 @@ void sdhci_enable_clk(struct sdhci_host *host, u16=
 clk)
>                 udelay(10);

This looks like it could be changed to an usleep_range(), perhaps an
additional change on top?

>         }
>
> +       clk |=3D SDHCI_CLOCK_PLL_EN;
> +       clk &=3D ~SDHCI_CLOCK_INT_STABLE;
> +       sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
> +
> +       /* Wait max 150 ms */
> +       timeout =3D ktime_add_ms(ktime_get(), 150);
> +       while (!((clk =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL))
> +               & SDHCI_CLOCK_INT_STABLE)) {
> +               if (ktime_after(ktime_get(), timeout)) {
> +                       pr_err("%s: PLL clock never stabilised.\n",
> +                              mmc_hostname(host->mmc));
> +                       sdhci_dumpregs(host);
> +                       return;
> +               }
> +               udelay(10);

Ditto.

> +       }
> +
>         clk |=3D SDHCI_CLOCK_CARD_EN;
>         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
> +
> +       mdelay(1);

This is new, maybe add a comment and change to usleep_range().

>  }
>  EXPORT_SYMBOL_GPL(sdhci_enable_clk);
>
> --
> 2.22.0
>
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If you want me to apply the patch, you have to drop the above notice.

Kind regards
Uffe