Received: by 2002:a25:ad19:0:0:0:0:0 with SMTP id y25csp9596852ybi; Wed, 24 Jul 2019 06:50:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqwe2wUMY6Yps4RjTFEnCc7FsqdFoWiUIRoLINkaX9mnu7KpfUk6v388yjpB6xxeg9+VOXZu X-Received: by 2002:aa7:9217:: with SMTP id 23mr11641897pfo.239.1563976245424; Wed, 24 Jul 2019 06:50:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1563976245; cv=none; d=google.com; s=arc-20160816; b=MLd3VeYZ8LVZgR2uDY5TA/sOr9XdMwCgxfItJ1B36oBqBP4O/RNJQWopWaS2GfCdtb HsRZYeKPmAO+0vdOLanCwGu7y7fThTL5RiYtX03a4AJev4nbDR25gu5ERIudUpNqSZlz MK0bbqJbGSIesE9LyZ8mMQT0oPfwdF9+mS6E4qceE0PojaW0wTsAT+BndzjHuovCzsDy 737WdU3SpAsawQzT51XK15Ads8blDk/M79ItxqXNV134NbwIBshQ5KihqexebJ7SWYwS q9n6PQeU3kY4ICTN0Hlq9Fnn/2SW4Zpnpu7ugeMY16AceaDIFNsF+WTTxKH6oPHwBwuv 2X4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:references:in-reply-to:subject :cc:to:from:date:content-transfer-encoding:mime-version; bh=jV9PFK4aVJClyf3cYfxQB1wra5AuOmqNt3GWwFOoMV0=; b=JV2nYGqvFEUgyLSByB7eHoXk4LGWL9Dts7F9zLeRlD4wFdjRH0t9qAOg1XWJ87vOB3 RLroUs9bzlQRbetGo1f5AJyGCkp7gpSSNaxr2g2NKxUkOZjBUZj8wpPcrxgUSKrn8loY P2upo2AQmcP0C5+wTWlO2Ey3ncaF6GTiOqkq+1bGWAR2rggAJzv8j3eN829DZ6Hi2Hl5 rPLgIiDeZBYl5W/tdPeT5BvjHXjjWT61kfMkuGeP8spCurefaG5HQ/4EjilV+2ZMrl22 ELfX6bzC8Nr57YIjQT+5IeLm+T867JW+Dpe/Lrf+oggxw7dfjzTO0Yt3nDCk1wNekcgO 7+hA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q67si27930601pgq.83.2019.07.24.06.50.30; Wed, 24 Jul 2019 06:50:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387458AbfGXNJE (ORCPT + 99 others); Wed, 24 Jul 2019 09:09:04 -0400 Received: from hermes.aosc.io ([199.195.250.187]:51846 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726535AbfGXNJD (ORCPT ); Wed, 24 Jul 2019 09:09:03 -0400 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 9615D6DF8F; Wed, 24 Jul 2019 13:09:01 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Date: Wed, 24 Jul 2019 21:09:01 +0800 From: Icenowy Zheng To: Maxime Ripard Cc: devicetree@vger.kernel.org, Linus Walleij , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, Rob Herring , Chen-Yu Tsai , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board In-Reply-To: <20190722192934.3jaf3r4rnyeslqyw@flea> References: <20190713034634.44585-1-icenowy@aosc.io> <20190713034634.44585-8-icenowy@aosc.io> <20190720101318.cwrvv5r42wxx5k4r@flea> <20190722192934.3jaf3r4rnyeslqyw@flea> Message-ID: <7d24576697521f4985617113dbc4cc41@aosc.io> X-Sender: icenowy@aosc.io Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 在 2019-07-23 03:29,Maxime Ripard 写道: > On Sat, Jul 20, 2019 at 07:39:08PM +0800, Icenowy Zheng wrote: >> >> >> 于 2019年7月20日 GMT+08:00 下午6:13:18, Maxime Ripard >> 写到: >> >On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote: >> >> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB >> >> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI >> >Flash. >> >> It has a gold finger connector for expansion, and UART is available >> >from >> >> reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or >> >> Allwinner V3L SoCs. >> >> >> >> Add the device tree binding of the basic version of the core board -- >> >> w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. >> >> >> >> Signed-off-by: Icenowy Zheng >> >> --- >> >> No changes since v3. >> >> >> >> Patch introduced in v2. >> >> >> >> Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ >> >> 1 file changed, 5 insertions(+) >> >> >> >> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml >> >b/Documentation/devicetree/bindings/arm/sunxi.yaml >> >> index 000a00d12d6a..48c126a7a848 100644 >> >> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml >> >> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml >> >> @@ -353,6 +353,11 @@ properties: >> >> - const: licheepi,licheepi-zero >> >> - const: allwinner,sun8i-v3s >> >> >> >> + - description: Lichee Zero Plus (with S3, without eMMC/SPI >> >Flash) >> >> + items: >> >> + - const: sipeed,lichee-zero-plus >> >> + - const: allwinner,sun8i-s3 >> > >> >If the S3 is just a rebranded V3, then we should have the v3 compatile >> >in that list too. >> >> S3 is V3 with copackaged DDR3 DRAM. >> >> It's pin incompatible w/ V3. > > Does it matter though? > > If the only thing that changes is the package, we're not manipulating > that, and any software that deals with the v3 can deal with the > s3. Which is what the compatible is about. Okay. Should the S3 compatible be kept befoer the V3 one? > > Maxime > > -- > Maxime Ripard, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel