Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
From:   Paul Cercueil <paul@crapouillou.net>
To:     Ralf Baechle <ralf@linux-mips.org>,
        Paul Burton <paul.burton@mips.com>,
        James Hogan <jhogan@kernel.org>
Cc:     linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
        od@zcrc.me, Paul Cercueil <paul@crapouillou.net>
Subject: [PATCH] MIPS: Add support for partial kernel mode on Xburst CPUs
Date:   Wed, 24 Jul 2019 19:46:54 -0400
Message-Id: <20190724234654.16555-1-paul@crapouillou.net>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

Support partial kernel mode of Xburst CPUs found in Ingenic SoCs.
Partial kernel mode means the userspace applications have access to
the TCSM0 banks of the VPU, and can execute cache instructions.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 arch/mips/Kconfig                | 7 +++++++
 arch/mips/include/asm/mipsregs.h | 1 +
 arch/mips/kernel/cpu-probe.c     | 4 ++++
 3 files changed, 12 insertions(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ac9ed08a7fff..02831908d676 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2986,6 +2986,13 @@ config MIPS_O32_FP64_SUPPORT
 
 	  If unsure, say N.
 
+config MIPS_XBURST_PARTIAL_KERNEL_MODE
+	bool "Partial kernel mode for Xburst CPUs" if MACH_INGENIC
+	help
+	  Support partial kernel mode of Xburst CPUs found in Ingenic SoCs.
+	  Partial kernel mode means the userspace applications have access to
+	  the TCSM0 banks of the VPU, and can execute cache instructions.
+
 config USE_OF
 	bool
 	select OF
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 1e6966e8527e..01e0fcb1d4c2 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -2813,6 +2813,7 @@ __BUILD_SET_C0(status)
 __BUILD_SET_C0(cause)
 __BUILD_SET_C0(config)
 __BUILD_SET_C0(config5)
+__BUILD_SET_C0(config7)
 __BUILD_SET_C0(intcontrol)
 __BUILD_SET_C0(intctl)
 __BUILD_SET_C0(srsmap)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index a9c82338396a..fd275f37cb7c 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1985,6 +1985,10 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 	 */
 	if ((c->processor_id & PRID_COMP_MASK) == PRID_COMP_INGENIC_D0)
 		c->isa_level &= ~MIPS_CPU_ISA_M32R2;
+
+	/* config7 bit 6 controls the "partial kernel mode" */
+	if (IS_ENABLED(CONFIG_MIPS_XBURST_PARTIAL_KERNEL_MODE))
+		set_c0_config7(BIT(6));
 }
 
 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
-- 
2.21.0.593.g511ec345e18