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Date:   Thu, 25 Jul 2019 09:50:31 +0200
From:   Peter Zijlstra <peterz@infradead.org>
To:     "Liang, Kan" <kan.liang@linux.intel.com>
Cc:     Yunying Sun <yunying.sun@intel.com>, mingo@redhat.com,
        acme@kernel.org, alexander.shishkin@linux.intel.com,
        jolsa@redhat.com, namhyung@kernel.org, tglx@linutronix.de,
        bp@alien8.de, hpa@zytor.com, ak@linux.intel.com, x86@kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH RESEND] perf/x86/intel: Bit 13 is valid for Icelake
 MSR_OFFCORE_RSP_x register
Message-ID: <20190725075031.GG31381@hirez.programming.kicks-ass.net>
References: <20190724073911.12177-1-yunying.sun@intel.com>
 <20190724082932.12833-1-yunying.sun@intel.com>
 <1022fe65-0f9a-52d3-2765-25aa2a326848@linux.intel.com>
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On Wed, Jul 24, 2019 at 09:11:01AM -0400, Liang, Kan wrote:
> 
> 
> On 7/24/2019 4:29 AM, Yunying Sun wrote:
> >  From Intel SDM, bit 13 of Icelake MSR_OFFCORE_RSP_x register is valid for
> > counting hardware generated prefetches of L3 cache. But current bitmasks
> > in driver takes bit 13 as invalid. Here to fix it.
> > 
> > Before:
> > $ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
> >   Performance counter stats for 'sleep 3':
> >     <not supported>      cpu/event=0xb7,umask=0x1,config1=0x1bfff/u
> > 
> > After:
> > $ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
> >   Performance counter stats for 'sleep 3':
> >               9,293      cpu/event=0xb7,umask=0x1,config1=0x1bfff/u
> > 
> > Signed-off-by: Yunying Sun <yunying.sun@intel.com>
> 
> Thanks Yunying.
> 
> Reviewed-by: Kan Liang <kan.liang@linux.intel.com>

Thanks!