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 <20190723122016.30279-1-a.swigon@partner.samsung.com> <20190723122016.30279-9-a.swigon@partner.samsung.com>
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Reply-To: cwchoi00@gmail.com
From:   Chanwoo Choi <cwchoi00@gmail.com>
Date:   Thu, 25 Jul 2019 22:13:29 +0900
Message-ID: <CAGTfZH1_Qk+vNa_AJW_8OA8MJbnZa3yCTLLRs2w23bNTm72gyQ@mail.gmail.com>
Subject: Re: [RFC PATCH 08/11] arm: dts: exynos: Add parents and
 #interconnect-cells to Exynos4412
To:     =?UTF-8?B?QXJ0dXIgxZp3aWdvxYQ=?= <a.swigon@partner.samsung.com>
Cc:     devicetree <devicetree@vger.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
        linux-samsung-soc <linux-samsung-soc@vger.kernel.org>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        Linux PM list <linux-pm@vger.kernel.org>,
        dri-devel <dri-devel@lists.freedesktop.org>,
        Krzysztof Kozlowski <krzk@kernel.org>,
        Chanwoo Choi <cw00.choi@samsung.com>,
        MyungJoo Ham <myungjoo.ham@samsung.com>, inki.dae@samsung.com,
        Seung-Woo Kim <sw0312.kim@samsung.com>,
        georgi.djakov@linaro.org,
        Marek Szyprowski <m.szyprowski@samsung.com>
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2019=EB=85=84 7=EC=9B=94 24=EC=9D=BC (=EC=88=98) =EC=98=A4=EC=A0=84 8:07, A=
rtur =C5=9Awigo=C5=84 <a.swigon@partner.samsung.com>=EB=8B=98=EC=9D=B4 =EC=
=9E=91=EC=84=B1:
>
> This patch adds two fields tp the Exynos4412 DTS:
>   - parent: to declare connections between nodes that are not in a
>     parent-child relation in devfreq;
>   - #interconnect-cells: required by the interconnect framework.
>
> Please note that #interconnect-cells is always zero and node IDs are not
> hardcoded anywhere.
>
> Signed-off-by: Artur =C5=9Awigo=C5=84 <a.swigon@partner.samsung.com>
> ---
>  arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 1 +
>  arch/arm/boot/dts/exynos4412.dtsi               | 9 +++++++++
>  2 files changed, 10 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/b=
oot/dts/exynos4412-odroid-common.dtsi
> index ea55f377d17c..bdd61ae86103 100644
> --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
> +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
> @@ -106,6 +106,7 @@
>  &bus_leftbus {
>         devfreq-events =3D <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
>         vdd-supply =3D <&buck3_reg>;
> +       parent =3D <&bus_dmc>;

It is wrong. 'bus_leftbus' has not any h/w dependency of 'bus_dmc'
and 'bus_leftbus' is not child of 'bus_dmc'.

Even it there are some PMQoS requirement between them,
it it not proper to tie both 'bus_leftbus' and 'bus_dmc'.

>         status =3D "okay";
>  };
>
> diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos=
4412.dtsi
> index d20db2dfe8e2..a70a671acacd 100644
> --- a/arch/arm/boot/dts/exynos4412.dtsi
> +++ b/arch/arm/boot/dts/exynos4412.dtsi
> @@ -390,6 +390,7 @@
>                         clocks =3D <&clock CLK_DIV_DMC>;
>                         clock-names =3D "bus";
>                         operating-points-v2 =3D <&bus_dmc_opp_table>;
> +                       #interconnect-cells =3D <0>;
>                         status =3D "disabled";
>                 };
>
> @@ -398,6 +399,7 @@
>                         clocks =3D <&clock CLK_DIV_ACP>;
>                         clock-names =3D "bus";
>                         operating-points-v2 =3D <&bus_acp_opp_table>;
> +                       #interconnect-cells =3D <0>;
>                         status =3D "disabled";
>                 };
>
> @@ -406,6 +408,7 @@
>                         clocks =3D <&clock CLK_DIV_C2C>;
>                         clock-names =3D "bus";
>                         operating-points-v2 =3D <&bus_dmc_opp_table>;
> +                       #interconnect-cells =3D <0>;
>                         status =3D "disabled";
>                 };
>
> @@ -459,6 +462,7 @@
>                         clocks =3D <&clock CLK_DIV_GDL>;
>                         clock-names =3D "bus";
>                         operating-points-v2 =3D <&bus_leftbus_opp_table>;
> +                       #interconnect-cells =3D <0>;
>                         status =3D "disabled";
>                 };
>
> @@ -467,6 +471,7 @@
>                         clocks =3D <&clock CLK_DIV_GDR>;
>                         clock-names =3D "bus";
>                         operating-points-v2 =3D <&bus_leftbus_opp_table>;
> +                       #interconnect-cells =3D <0>;
>                         status =3D "disabled";
>                 };
>
> @@ -475,6 +480,7 @@
>                         clocks =3D <&clock CLK_ACLK160>;
>                         clock-names =3D "bus";
>                         operating-points-v2 =3D <&bus_display_opp_table>;
> +                       #interconnect-cells =3D <0>;
>                         status =3D "disabled";
>                 };
>
> @@ -483,6 +489,7 @@
>                         clocks =3D <&clock CLK_ACLK133>;
>                         clock-names =3D "bus";
>                         operating-points-v2 =3D <&bus_fsys_opp_table>;
> +                       #interconnect-cells =3D <0>;
>                         status =3D "disabled";
>                 };
>
> @@ -491,6 +498,7 @@
>                         clocks =3D <&clock CLK_ACLK100>;
>                         clock-names =3D "bus";
>                         operating-points-v2 =3D <&bus_peri_opp_table>;
> +                       #interconnect-cells =3D <0>;
>                         status =3D "disabled";
>                 };
>
> @@ -499,6 +507,7 @@
>                         clocks =3D <&clock CLK_SCLK_MFC>;
>                         clock-names =3D "bus";
>                         operating-points-v2 =3D <&bus_leftbus_opp_table>;
> +                       #interconnect-cells =3D <0>;
>                         status =3D "disabled";
>                 };
>
> --
> 2.17.1
>


--=20
Best Regards,
Chanwoo Choi