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From:   Jayachandran Chandrasekharan Nair <jnair@marvell.com>
To:     Bjorn Helgaas <helgaas@kernel.org>
CC:     Shannon Zhao <shenglong.zsl@alibaba-inc.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        Guiping Duan <gduan@marvell.com>,
        George Cherian <gcherian@marvell.com>,
        "Sunil Kovvuri Goutham" <sgoutham@marvell.com>
Subject: Re: [PATCH] PCI: Add ACS quirk for Cavium ThunderX 2 root port
 devices
Thread-Topic: [PATCH] PCI: Add ACS quirk for Cavium ThunderX 2 root port
 devices
Thread-Index: AQHVQwboV84qzPxVD0yOX55pKvzUPQ==
Date:   Thu, 25 Jul 2019 16:35:02 +0000
Message-ID: <20190725163453.GA28724@dc5-eodlnx05.marvell.com>
References: <1563541835-141011-1-git-send-email-shenglong.zsl@alibaba-inc.com>
 <20190724185535.GD203187@google.com>
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On Wed, Jul 24, 2019 at 01:55:35PM -0500, Bjorn Helgaas wrote:
> See
> https://lkml.kernel.org/r/20171026223701.GA25649@bhelgaas-glaptop.roam.co=
rp.google.com
> for incidental hints (subject, commit log, commit reference).  Your
> patch basically extends that commit, so the subject should be very
> similar.
>=20
> On Fri, Jul 19, 2019 at 09:10:35PM +0800, Shannon Zhao wrote:
> > From: Shannon Zhao <shannon.zhao@linux.alibaba.com>
> >=20
> > Like commit f2ddaf8(PCI: Apply Cavium ThunderX ACS quirk to more Root
> > Ports), it should apply ACS quirk to ThunderX 2 root port devices.
>=20
> s/root port/Root Port/ to be consistent
>=20
> > Signed-off-by: Shannon Zhao <shannon.zhao@linux.alibaba.com>
>=20
> I suppose this should have the same stable tag as f2ddaf8dfd4a ("PCI:
> Apply Cavium ThunderX ACS quirk to more Root Ports") itself?
> > ---
> >  drivers/pci/quirks.c | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> >=20
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> > index 28c64f8..ea7848b 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -4224,10 +4224,12 @@ static bool pci_quirk_cavium_acs_match(struct p=
ci_dev *dev)
> >  	 * family by 0xf800 mask (which represents 8 SoCs), while the lower
> >  	 * bits of device ID are used to indicate which subdevice is used
> >  	 * within the SoC.
> > +	 * Effectively selects the ThunderX 2 root ports whose device ID
> > +	 * is 0xaf84.
> >  	 */
> >  	return (pci_is_pcie(dev) &&
> >  		(pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_ROOT_PORT) &&
> > -		((dev->device & 0xf800) =3D=3D 0xa000));
> > +		((dev->device & 0xf800) =3D=3D 0xa000 || dev->device =3D=3D 0xaf84))=
;
>=20
> I'm somewhat doubtful about this because previously we at least
> selected a whole class of ThunderX 1 devices:
>=20
>   ((dev->device & 0xf800) =3D=3D 0xa000)
>=20
> while you're adding only a *single* ThunderX device.
>=20
> I don't want a constant trickle of adding new devices.  Can somebody
> from Cavium or Marvell provide a corresponding mask for ThunderX 2, or
> confirm that 0xaf84 is really the single device we expect to need
> here?
=20
We are working on a patch to fix this quirk to handle more Marvell
(Cavium) PCI IDs. Ideally we should be handling ThunderX1, ThunderX2
and the Octeon-TX families here.

Adding the folks working on this reduce the churn here, hopefully
we can get all of it sorted in one patch.
=20
JC