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From:   Paul Burton <paul.burton@mips.com>
To:     Paul Cercueil <paul@crapouillou.net>
CC:     Ralf Baechle <ralf@linux-mips.org>,
        James Hogan <jhogan@kernel.org>,
        "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "od@zcrc.me" <od@zcrc.me>
Subject: Re: [PATCH] MIPS: Add support for partial kernel mode on Xburst CPUs
Thread-Topic: [PATCH] MIPS: Add support for partial kernel mode on Xburst CPUs
Thread-Index: AQHVQwpUGZILpjjRRkOL6x5V3OyS8w==
Date:   Thu, 25 Jul 2019 16:59:31 +0000
Message-ID: <20190725165930.yvlvmavcgqocl3nn@pburton-laptop>
References: <20190724234654.16555-1-paul@crapouillou.net>
In-Reply-To: <20190724234654.16555-1-paul@crapouillou.net>
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Hi Paul,

On Wed, Jul 24, 2019 at 07:46:54PM -0400, Paul Cercueil wrote:
> Support partial kernel mode of Xburst CPUs found in Ingenic SoCs.
> Partial kernel mode means the userspace applications have access to
> the TCSM0 banks of the VPU,

So far so (reasonably) good :)

> and can execute cache instructions.

Aaaah! Scary!

Does this allow *all* cache instructions? If so that's a big security &
stability hole - if userland can invalidate kernel data or data from
other programs then it can create all sorts of chaos.

Also do you know which Ingenic SoCs this is available on? I see it
documented in the JZ4780 Programming Manual, but Config7 bit 6 is shown
as reserved in my copy of the XBurst1 CPU Core Programming Manual.

I notice the JZ4780 documentation says it allows access "including TCSM,
CACHE instructions" which is scary too since it doesn't say that's *all*
it allows access to. Though just cache instructions by themselves are
enough to be game over for any notion of security as mentioned above.

What is it you want to do with this? I'm wondering if we could achieve
your goal is in a safer way.

Thanks,
    Paul