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[209.132.180.67]) by mx.google.com with ESMTP id r72si17313426pjb.33.2019.07.26.02.22.42; Fri, 26 Jul 2019 02:22:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726606AbfGZJVv (ORCPT + 99 others); Fri, 26 Jul 2019 05:21:51 -0400 Received: from honk.sigxcpu.org ([24.134.29.49]:59368 "EHLO honk.sigxcpu.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726519AbfGZJVs (ORCPT ); Fri, 26 Jul 2019 05:21:48 -0400 Received: from localhost (localhost [127.0.0.1]) by honk.sigxcpu.org (Postfix) with ESMTP id B11E3FB05; Fri, 26 Jul 2019 11:21:46 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at honk.sigxcpu.org Received: from honk.sigxcpu.org ([127.0.0.1]) by localhost (honk.sigxcpu.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZTomQ0x7jPSO; Fri, 26 Jul 2019 11:21:43 +0200 (CEST) Received: by bogon.sigxcpu.org (Postfix, from userid 1000) id 3348346A9D; Fri, 26 Jul 2019 11:21:43 +0200 (CEST) From: =?UTF-8?q?Guido=20G=C3=BCnther?= To: =?UTF-8?q?Guido=20G=C3=BCnther?= , Purism Kernel Team , Thierry Reding , Sam Ravnborg , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] drm/panel: jh057n00900: Move panel DSI init to enable() Date: Fri, 26 Jul 2019 11:21:41 +0200 Message-Id: <965bed10ddfc6c14d074520d55bde7bb1ffce5d1.1564132646.git.agx@sigxcpu.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org If the panel is wrapped in a panel_bridge it gets prepar()ed before the upstream DSI bridge which can cause hangs (e.g. with imx-nwl since clocks are not enabled yet). To avoid this move the panel's first DSI access to enable() so the upstream bridge can prepare the DSI host controller in it's pre_enable(). This is also in line with other panel drivers. Signed-off-by: Guido Günther --- .../gpu/drm/panel/panel-rocktech-jh057n00900.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-rocktech-jh057n00900.c b/drivers/gpu/drm/panel/panel-rocktech-jh057n00900.c index 1274b54f2672..c6b4bfd79fde 100644 --- a/drivers/gpu/drm/panel/panel-rocktech-jh057n00900.c +++ b/drivers/gpu/drm/panel/panel-rocktech-jh057n00900.c @@ -143,6 +143,14 @@ static int jh057n_init_sequence(struct jh057n *ctx) static int jh057n_enable(struct drm_panel *panel) { struct jh057n *ctx = panel_to_jh057n(panel); + int ret; + + ret = jh057n_init_sequence(ctx); + if (ret < 0) { + DRM_DEV_ERROR(ctx->dev, "Panel init sequence failed: %d\n", + ret); + return ret; + } return backlight_enable(ctx->backlight); } @@ -197,13 +205,6 @@ static int jh057n_prepare(struct drm_panel *panel) gpiod_set_value_cansleep(ctx->reset_gpio, 0); msleep(20); - ret = jh057n_init_sequence(ctx); - if (ret < 0) { - DRM_DEV_ERROR(ctx->dev, "Panel init sequence failed: %d\n", - ret); - return ret; - } - ctx->prepared = true; return 0; -- 2.20.1