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[209.132.180.67]) by mx.google.com with ESMTP id q14si20717693pgm.325.2019.07.26.12.22.37; Fri, 26 Jul 2019 12:22:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=U88KFzuV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726888AbfGZQSz (ORCPT + 99 others); Fri, 26 Jul 2019 12:18:55 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:52813 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726007AbfGZQSy (ORCPT ); Fri, 26 Jul 2019 12:18:54 -0400 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x6QG6Hpo030144; Fri, 26 Jul 2019 18:18:39 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=subject : to : cc : references : from : message-id : date : mime-version : in-reply-to : content-type : content-transfer-encoding; s=STMicroelectronics; bh=IXxLWvTNmiUU59JMUeszE0o+fXSHf9wp+bJ4iqAv/do=; b=U88KFzuVSXQpIKzDDIIFqcilRxMXyICiEVyjCMNY+rbxk9rSKnFDcH/P278PPIbd4rLf aPDtJWnkFTk9gQFloRyeusVw4Dx/TADtO+SHjPK2xrfnFjXoc0gGkfxP8zWKu7IN5wFh AiC+yx8mYfw3irtzXVPlv690ZPfQvA1xaKmmxypjVC2uIeQC6vfR9w8T6W4QnM85zDet wWQNU8sEubADekjpmE28/XSiEcRq/cGjNXAqKvvmfW5X3HCC/8IJOIOffSRUpFb9yljP CuB400jQn4GQzeKNj69eW6R8Okf8JVlYPImBfQCVDv7HKdhS2zXXb62smI2pbOKo8rhJ bA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2tx604bj0f-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 26 Jul 2019 18:18:39 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 08D2E31; Fri, 26 Jul 2019 16:18:39 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag3node2.st.com [10.75.127.8]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D00874FB7; Fri, 26 Jul 2019 16:18:38 +0000 (GMT) Received: from lmecxl0912.lme.st.com (10.75.127.48) by SFHDAG3NODE2.st.com (10.75.127.8) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 26 Jul 2019 18:18:37 +0200 Subject: Re: [PATCH v4 0/8] stm32 m4 remoteproc on STM32MP157c To: Fabien Dessenne , Rob Herring , Mark Rutland , Maxime Coquelin , Ohad Ben-Cohen , Bjorn Andersson , , , , , CC: Loic Pallardy , Arnaud Pouliquen , Ludovic Barre , Benjamin Gaignard References: <1557822423-22658-1-git-send-email-fabien.dessenne@st.com> From: Alexandre Torgue Message-ID: <334f2829-fa5e-3f81-5872-730b2aa8b757@st.com> Date: Fri, 26 Jul 2019 18:18:37 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <1557822423-22658-1-git-send-email-fabien.dessenne@st.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SFHDAG3NODE2.st.com (10.75.127.8) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-07-26_12:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Fabien On 5/14/19 10:26 AM, Fabien Dessenne wrote: > STMicrolectronics STM32MP157 MPU are based on a Dual Arm Cortex-A7 core and a > Cortex-M4. > This patchset adds the support of the stm32_rproc driver allowing to control > the M4 remote processor. > ... > driver > remoteproc: stm32: add an ST stm32_rproc driver > ARM: dts: stm32: add m4 remoteproc support on STM32MP157c > ARM: dts: stm32: declare copro reserved memories on STM32MP157c-ed1 > ARM: dts: stm32: enable m4 coprocessor support on STM32MP157c-ed1 > ARM: dts: stm32: declare copro reserved memories on STM32MP157a-dk1 > ARM: dts: stm32: enable m4 coprocessor support on STM32MP157a-dk1 > DT patches applied on stm32-next. Regards Alexandre