Received: by 2002:a25:ad19:0:0:0:0:0 with SMTP id y25csp1845374ybi; Sat, 27 Jul 2019 20:16:39 -0700 (PDT) X-Google-Smtp-Source: APXvYqyJ8Zzv6MswYmDHOLU/EtvE9lfC//OZAy+Bd6hvUIYNchhDIuCDvYj1fi1mQLjLQvHlkCmT X-Received: by 2002:a17:902:2929:: with SMTP id g38mr83358888plb.163.1564283799744; Sat, 27 Jul 2019 20:16:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564283799; cv=none; d=google.com; s=arc-20160816; b=Xh9lgH0DWijtAYW2qRYyoHQVZEZv4/7uoX6NDeIGWUI5DQAAnAVClCClJqiDzO58a/ 20uKYHYimIPz0as9BSz4PT3dowfnx3SEeZ9NexwVIZcnWM8fpWpeeYj6ITLFsM7nqnkq eWZj/Q272N6flgr10YOY11PlsbfE1GLtUyxIAHhZ86P5d6Cbmj0/L613WOeQ8WRlgxZ0 +SW4e6cdaAYOWLQvF0uzrD83m4pyDbFhW2EXqdL7UEnbZlDu9I8ElIoK9E7UMw+EcncI WRGi4aQl4EvLBf2/rdwIGfYkKKT8deLPDH/EXgDXS50m7fIAQzuAGVoEiX+zpfXB+Q9O lmzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=sJgnxXx4smiNEUratZftQYmp67JOB0CB5exVmxZLbLE=; b=ikY7gq95KKiJuD8LpvvVe4GudtUNs9TtqyBtkknZo/crrMd3AYNqR3YkfnVjHjccm1 BZbIUUMRWQjnfwTEijJnUpM2ve8bXjy6DcWmvTFe2+dzcQILN+XuAb2M86CP9sMYRKv4 50yEcwGr/ifflTHITDEDUBw+DMtbaZ5AQwzUvHkyaphtPP4R1Wyc6rIbqG4JnhKgLJRP VFIFNZcU9SvOvswOBEwTzGsfPq61DDlTkFw5dR3rZsVDwV5ybjMDlnKanVhlyZaRJLrh 8F3EfGcD4kv4tS5bsKSJPR6OYX+3Dt+GtqU/3mCwaFwqpF+8ZVjiOTzSp9mPztr2mkhy 5Bhw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u18si20862106plq.311.2019.07.27.20.15.42; Sat, 27 Jul 2019 20:16:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726208AbfG1DNz (ORCPT + 99 others); Sat, 27 Jul 2019 23:13:55 -0400 Received: from hermes.aosc.io ([199.195.250.187]:52376 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725440AbfG1DNz (ORCPT ); Sat, 27 Jul 2019 23:13:55 -0400 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id CB4BF6F8D3; Sun, 28 Jul 2019 03:13:51 +0000 (UTC) From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Linus Walleij Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [PATCH v5 2/6] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks Date: Sun, 28 Jul 2019 11:12:23 +0800 Message-Id: <20190728031227.49140-3-icenowy@aosc.io> In-Reply-To: <20190728031227.49140-1-icenowy@aosc.io> References: <20190728031227.49140-1-icenowy@aosc.io> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The MMC2 clock slices are currently not defined in V3s CCU driver, which makes MMC2 not working. Fix this issue. Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU") Signed-off-by: Icenowy Zheng --- Changes in v5: - Fix typo on hw_clk reference. Patch introduced in v4. drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c index 4eb68243e310..f79170e145df 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c @@ -513,6 +513,9 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = { [CLK_MMC1] = &mmc1_clk.common.hw, [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, + [CLK_MMC2] = &mmc2_clk.common.hw, + [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw, + [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw, [CLK_CE] = &ce_clk.common.hw, [CLK_SPI0] = &spi0_clk.common.hw, [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, -- 2.21.0