Subject: Re: [discuss] [patch] x86_64:  align and pad x86_64 GDT on page
	boundary
From: Rohit Seth <rohit.seth@intel.com>
To: Andi Kleen <ak@suse.de>
Cc: Ravikiran G Thirumalai <kiran@scalex86.org>, Andrew Morton <akpm@osdl.org>,
       linux-kernel@vger.kernel.org, discuss@x86-64.org, zach@vmware.com,
       shai@scalex86.org, nippung@calsoftinc.com
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	 <1134083357.7131.21.camel@akash.sc.intel.com>
	 <20051208231141.GX11190@wotan.suse.de>
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Organization: Intel 
Date: Thu, 08 Dec 2005 15:26:07 -0800
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On Fri, 2005-12-09 at 00:11 +0100, Andi Kleen wrote:
> On Thu, Dec 08, 2005 at 03:09:17PM -0800, Rohit Seth wrote:
> >
> > IIRC, Zach's patches for gdt alignment, moved the gdts from per_cpu data
> > structure to each secondary CPU dynamically allocating page for its gdt.
> 
> Kiran's patch does this too.  Except for the BP GDT, which could
> be shared with the single IDT.
> 

...that padding in BP's GDT (in this and original patches) could be
because of the Xen requirements to have dedicated pages for gdt.

-rohit


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