Date: Fri, 9 Dec 2005 00:26:10 +0100
From: Andi Kleen <ak@suse.de>
To: Rohit Seth <rohit.seth@intel.com>
Cc: Andi Kleen <ak@suse.de>, Ravikiran G Thirumalai <kiran@scalex86.org>,
       Andrew Morton <akpm@osdl.org>, linux-kernel@vger.kernel.org,
       discuss@x86-64.org, zach@vmware.com, shai@scalex86.org,
       nippung@calsoftinc.com
Subject: Re: [discuss] [patch] x86_64:  align and pad x86_64 GDT on page boundary
Message-ID: <20051208232610.GY11190@wotan.suse.de>
References: <20051208215514.GE3776@localhost.localdomain> <1134083357.7131.21.camel@akash.sc.intel.com> <20051208231141.GX11190@wotan.suse.de> <1134084367.7131.32.camel@akash.sc.intel.com>
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On Thu, Dec 08, 2005 at 03:26:07PM -0800, Rohit Seth wrote:
> On Fri, 2005-12-09 at 00:11 +0100, Andi Kleen wrote:
> > On Thu, Dec 08, 2005 at 03:09:17PM -0800, Rohit Seth wrote:
> > >
> > > IIRC, Zach's patches for gdt alignment, moved the gdts from per_cpu data
> > > structure to each secondary CPU dynamically allocating page for its gdt.
> > 
> > Kiran's patch does this too.  Except for the BP GDT, which could
> > be shared with the single IDT.
> > 
> 
> ...that padding in BP's GDT (in this and original patches) could be
> because of the Xen requirements to have dedicated pages for gdt.

Well if the Xen people have such requirements they can submit
separate patches. Currently they don't seem to be interested
at all in submitting patches to mainline, so we must work
with the VM hackers who are interested in this (scalex86, VMware) 
And AFAIK they only care about not having false sharing in there.

-Andi

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