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Tue, 30 Jul 2019 19:07:31 +0000 From: "Shirley Her (SC)" To: "adrian.hunter@intel.com" , "ulf.hansson@linaro.org" , "linux-mmc@vger.kernel.org" , "linux-kernel@vger.kernel.org" CC: "Chevron Li (WH)" , "Louis Lu (TP)" , "Max Huang (SC)" , "Shirley Her (SC)" Subject: [PATCH V3 1/2] mmc: sdhci: Fix O2 Host data read/write DLL lock phase shift issue Thread-Topic: [PATCH V3 1/2] mmc: sdhci: Fix O2 Host data read/write DLL lock phase shift issue Thread-Index: AQHVRwoJNw6NuC9tc0Wwlz+CI0GUdA== Date: Tue, 30 Jul 2019 19:07:30 +0000 Message-ID: <1564513648-16377-1-git-send-email-shirley.her@bayhubtech.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR02CA0003.namprd02.prod.outlook.com (2603:10b6:a02:ee::16) To MWHPR16MB1455.namprd16.prod.outlook.com (2603:10b6:320:28::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=shirley.her@bayhubtech.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.7.4 x-originating-ip: [209.36.105.184] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 3e22db25-4685-40fb-2b7a-08d715212b9a x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(7021145)(8989299)(4534185)(7022145)(4603075)(4627221)(201702281549075)(8990200)(7048125)(7024125)(7027125)(7023125)(5600148)(711020)(4605104)(1401327)(2017052603328)(7193020);SRVR:MWHPR16MB1455; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: bayhubtech.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3e22db25-4685-40fb-2b7a-08d715212b9a X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Jul 2019 19:07:30.8754 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 0a7aae2b-8f2e-44df-ba2f-42de7f93c642 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: shirley.her@bayhubtech.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR16MB1455 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fix data read/write error in HS200 mode due to chip DLL lock phase shift Signed-off-by:Shirley Her --- change in V3: 1. add more explanation in dll_recovery and execute_tuning function 2. move dll_adjust_count to O2_host struct 3. fix some coding style error 4. renaming O2_PLL_WDT_CONTROL1 to O2_PLL_DLL_WDT_CONTROL1 change in V2: 1. use usleep_range instead of udelay 2. move dll_adjust_count to sdhci-pci-o2micro.com change in V1: 1. add error recovery function to relock DLL with correct phase 2. retunign HS200 after DLL locked --- drivers/mmc/host/sdhci-pci-o2micro.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-= pci-o2micro.c index 9dc4548..186a33d 100644 --- a/drivers/mmc/host/sdhci-pci-o2micro.c +++ b/drivers/mmc/host/sdhci-pci-o2micro.c @@ -51,7 +51,7 @@ #define O2_SD_VENDOR_SETTING2 0x1C8 #define O2_SD_HW_TUNING_DISABLE BIT(4) =20 -#define O2_PLL_WDT_CONTROL1 0x1CC +#define O2_PLL_DLL_WDT_CONTROL1 0x1CC #define O2_PLL_FORCE_ACTIVE BIT(18) #define O2_PLL_LOCK_STATUS BIT(14) #define O2_PLL_SOFT_RESET BIT(12) --=20 2.7.4