Received: by 2002:a25:ad19:0:0:0:0:0 with SMTP id y25csp5323655ybi; Tue, 30 Jul 2019 18:37:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqy8Ds6sQCifERROWV/0hQoGXu9owICWlNHDIuVgyYqnHU5mMRaQGX+Q5kELFr+wOUXybCX/ X-Received: by 2002:a17:902:7d86:: with SMTP id a6mr117829272plm.199.1564537045076; Tue, 30 Jul 2019 18:37:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564537045; cv=none; d=google.com; s=arc-20160816; b=d6aOyIH+21TPlpp0jBMWQbNmupLzXayHpFizk/yJVBSNUATSEa4bvI7IVJKLjK2xY/ /E5X661q/5Ap4uBDpkJfyP9FLiFlCCjMj+v7+5TFI6MpZwy7bUM9FHlMogSdu74E4sdw WveShza1Rfo0XZLPrWVlM84QxyZtz8w/O5+YrSkYzX8c5seACNPAvSwz3T2Ez4soYh18 PktljgrwBPxRr4V9BgX9Q4vvavBjKDU0HDzg6orD7cJmvXW47lKexYX827FDzueezOQB V+gWMjp7LmC9fl+LeruWqGJF9fDAXE2PfGIC52a7IRH/0NRuQh08FpGvJhL24XEoRMqD A9rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-disposition:mime-version:references:message-id:subject:cc :to:from:date; bh=P0et6mbQFASrMRRZbrxPsI0GcfmUTonSbqT5jLDhZt0=; b=IuwtKy91VFguMZMAcH410boqpUP+xpfNy1sBqB5ngV5N5BH9G0WYY0u1vvdVcSSAL2 SbWNU1mtLrkl3kpt1VGMgUNdZgiTrygirQsFzo4GPRkfpGCox30raNfaK2suc9DgPtMU a+lblDHrULvhKEjFrNYWbIN+9tlJcIHuo1gwJ6A1YF7iyPNl4TS7nN+znLk7vtql0hwZ ZVhiuN/UJisCtNBgpWdsYv2+0YZjIy2mTiNc8rVdb7i4Gom5LLTmwbaD8S6i9wjabRvq 7/Sh78KFAtqemykjBuO44fqPEYFYID3YB7Pop/pIBYNKgMaYHo3HmMFpndQeo3INcryt lBnw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 68si31341436pgb.104.2019.07.30.18.37.09; Tue, 30 Jul 2019 18:37:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726238AbfG3Tfe (ORCPT + 99 others); Tue, 30 Jul 2019 15:35:34 -0400 Received: from gate.crashing.org ([63.228.1.57]:35096 "EHLO gate.crashing.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725866AbfG3Tfd (ORCPT ); Tue, 30 Jul 2019 15:35:33 -0400 Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id x6UJZ30i024763; Tue, 30 Jul 2019 14:35:03 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id x6UJZ26C024762; Tue, 30 Jul 2019 14:35:02 -0500 X-Authentication-Warning: gate.crashing.org: segher set sender to segher@kernel.crashing.org using -f Date: Tue, 30 Jul 2019 14:35:02 -0500 From: Segher Boessenkool To: Arnd Bergmann Cc: Nathan Chancellor , Nick Desaulniers , Michael Ellerman , christophe leroy , kbuild test robot , Benjamin Herrenschmidt , Paul Mackerras , linuxppc-dev , Linux Kernel Mailing List , clang-built-linux Subject: Re: [PATCH] powerpc: workaround clang codegen bug in dcbz Message-ID: <20190730193502.GR31406@gate.crashing.org> References: <20190729202542.205309-1-ndesaulniers@google.com> <20190729203246.GA117371@archlinux-threadripper> <20190729215200.GN31406@gate.crashing.org> <20190730134856.GO31406@gate.crashing.org> <20190730161637.GP31406@gate.crashing.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.3i Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jul 30, 2019 at 08:24:14PM +0200, Arnd Bergmann wrote: > On Tue, Jul 30, 2019 at 6:16 PM Segher Boessenkool > wrote: > > in_le32 and friends? Yeah, huh. If LLVM copies that to the stack as > > well, its (not byte reversing) read will be atomic just fine, so things > > will still work correctly. > > byteorder is fine, the problem I was thinking of is when moving the load/store > instructions around the barriers that synchronize with DMA, or turning > them into different-size accesses. Changing two consecutive 16-bit mmio reads > into an unaligned 32-bit read will rarely have the intended effect ;-) Most such barriers will also work on the copy accesses, I think. But yes it depends on exactly how it is written. The {in,out}_{be,le} ones use sync;store for out and sync;load;trap;isync for in, so they should be safe ;-) (Well, almost -- writes to I/O will not necessarily actually happen before other stores, not from these macros alone at least). Should be pretty easy to check what LLVM makes of this? Segher