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[209.132.180.67]) by mx.google.com with ESMTP id q23si32746869pfc.179.2019.07.31.01.58.15; Wed, 31 Jul 2019 01:58:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=codethink.co.uk Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726785AbfGaI5b (ORCPT + 99 others); Wed, 31 Jul 2019 04:57:31 -0400 Received: from imap1.codethink.co.uk ([176.9.8.82]:38038 "EHLO imap1.codethink.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725857AbfGaI5b (ORCPT ); Wed, 31 Jul 2019 04:57:31 -0400 Received: from [167.98.27.226] (helo=[10.35.6.253]) by imap1.codethink.co.uk with esmtpsa (Exim 4.84_2 #1 (Debian)) id 1hskQ5-0003o4-QJ; Wed, 31 Jul 2019 09:57:13 +0100 Subject: Re: [alsa-devel] [PATCH v2 2/3] ASoC: Add codec driver for ST TDA7802 To: Marco Felsch Cc: Mark Rutland , devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Charles Keepax , Kuninori Morimoto , Kirill Marinushkin , linux-kernel@vger.kernel.org, Takashi Iwai , Annaliese McDermond , Liam Girdwood , Paul Cercueil , Rob Herring , Vinod Koul , Mark Brown , Srinivas Kandagatla , Patrick Glaser , Rob Duncan , Jerome Brunet , Nate Case , Cheng-Yi Chiang References: <20190730120937.16271-1-thomas.preston@codethink.co.uk> <20190730120937.16271-3-thomas.preston@codethink.co.uk> <20190730145844.GI4264@sirena.org.uk> <20190731060644.yrewu2kvrlootyyl@pengutronix.de> From: Thomas Preston Message-ID: <820e2ea9-14a2-795c-9b78-e8f2a30afdb1@codethink.co.uk> Date: Wed, 31 Jul 2019 09:57:12 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190731060644.yrewu2kvrlootyyl@pengutronix.de> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 31/07/2019 07:06, Marco Felsch wrote: > Hi Thomas, > > again sorry for jumping in.. > Np! > On 19-07-30 18:26, Thomas Preston wrote: >> On 30/07/2019 15:58, Mark Brown wrote: >>> On Tue, Jul 30, 2019 at 01:09:36PM +0100, Thomas Preston wrote: >>>> + case SND_SOC_BIAS_STANDBY: >>>> + err = regulator_enable(tda7802->enable_reg); >>>> + if (err < 0) { >>>> + dev_err(component->dev, "Could not enable.\n"); >>>> + return err; >>>> + } >>>> + dev_dbg(component->dev, "Regulator enabled\n"); >>>> + msleep(ENABLE_DELAY_MS); >>> >>> Is this delay needed by the device or is it for the regulator to ramp? >>> If it's for the regulator to ramp then the regulator should be doing it. >>> >> >> According to the datasheet the device itself takes 10ms to rise from 0V >> after PLLen is enabled. There are additional rise times but they are >> negligible with default capacitor configuration (which we have). >> >> Good to know about the regulator rising configuration though. Thanks. > > Isn't it the regulator we mentioned to not use that because it is a > GPIO? > Yeah it is - I intend to switch PLLen to gpio API.