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Wed, 31 Jul 2019 09:12:16 +0000 From: To: , , CC: , , , , , , Subject: [PATCH 5/6] mtd: spi-nor: Add s3an_post_sfdp_fixups() Thread-Topic: [PATCH 5/6] mtd: spi-nor: Add s3an_post_sfdp_fixups() Thread-Index: AQHVR4AMaH6Ddp0nkEGsW9FcCZCHsw== Date: Wed, 31 Jul 2019 09:12:16 +0000 Message-ID: <20190731091145.27374-6-tudor.ambarus@microchip.com> References: <20190731091145.27374-1-tudor.ambarus@microchip.com> In-Reply-To: <20190731091145.27374-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR08CA0130.eurprd08.prod.outlook.com (2603:10a6:800:d4::32) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.154] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 3b041976-7bf4-482e-d6a3-08d715972ea2 x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(2017052603328)(7193020);SRVR:MN2PR11MB4414; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 3b041976-7bf4-482e-d6a3-08d715972ea2 X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Jul 2019 09:12:16.4044 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: tudor.ambarus@microchip.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4414 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus s3an_nor_scan() was overriding the opcode selection done in spi_nor_default_setup(). Set nor->setup() method in order to avoid unnecessary call to spi_nor_default_setup(). Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 35 +++++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 0ff474e5e4f5..5fea5d7ce2cb 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -2795,7 +2795,9 @@ static int spi_nor_check(struct spi_nor *nor) return 0; } =20 -static int s3an_nor_scan(struct spi_nor *nor) +static int s3an_nor_setup(struct spi_nor *nor, + const struct spi_nor_flash_parameter *params, + const struct spi_nor_hwcaps *hwcaps) { int ret; u8 val; @@ -4393,6 +4395,11 @@ static void spansion_post_sfdp_fixups(struct spi_nor= *nor) nor->mtd.erasesize =3D nor->info->sector_size; } =20 +static void s3an_post_sfdp_fixups(struct spi_nor *nor) +{ + nor->setup =3D s3an_nor_setup; +} + static void spi_nor_manufacturer_post_sfdp_fixups(struct spi_nor *nor, struct spi_nor_flash_parameter *params) @@ -4405,6 +4412,9 @@ spi_nor_manufacturer_post_sfdp_fixups(struct spi_nor = *nor, default: break; } + + if (nor->info->flags & SPI_S3AN) + s3an_post_sfdp_fixups(nor); } =20 static void spi_nor_post_sfdp_fixups(struct spi_nor *nor, @@ -4582,9 +4592,9 @@ static int spi_nor_select_erase(struct spi_nor *nor, = u32 wanted_size) return 0; } =20 -static int spi_nor_setup(struct spi_nor *nor, - const struct spi_nor_flash_parameter *params, - const struct spi_nor_hwcaps *hwcaps) +static int spi_nor_default_setup(struct spi_nor *nor, + const struct spi_nor_flash_parameter *params, + const struct spi_nor_hwcaps *hwcaps) { u32 ignored_mask, shared_mask; int err; @@ -4641,6 +4651,16 @@ static int spi_nor_setup(struct spi_nor *nor, return err; } =20 +static int spi_nor_setup(struct spi_nor *nor, + const struct spi_nor_flash_parameter *params, + const struct spi_nor_hwcaps *hwcaps) +{ + if (!nor->setup) + return 0; + + return nor->setup(nor, params, hwcaps); +} + static int spi_nor_disable_write_protection(struct spi_nor *nor) { if (!nor->disable_write_protection) @@ -4804,6 +4824,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *nam= e, /* Kept only for backward compatibility purpose. */ nor->quad_enable =3D spansion_quad_enable; nor->set_4byte =3D spansion_set_4byte; + nor->setup =3D spi_nor_default_setup; =20 /* Default locking operations. */ if (info->flags & SPI_NOR_HAS_LOCK) { @@ -4905,12 +4926,6 @@ int spi_nor_scan(struct spi_nor *nor, const char *na= me, return -EINVAL; } =20 - if (info->flags & SPI_S3AN) { - ret =3D s3an_nor_scan(nor); - if (ret) - return ret; - } - /* Send all the required SPI flash commands to initialize device */ ret =3D spi_nor_init(nor); if (ret) --=20 2.9.5