Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Received-SPF: Pass (esa5.microchip.iphmx.com: domain of
  Tudor.Ambarus@microchip.com designates 198.175.253.82 as
  permitted sender) identity=mailfrom;
  client-ip=198.175.253.82; receiver=esa5.microchip.iphmx.com;
  envelope-from="Tudor.Ambarus@microchip.com";
  x-sender="Tudor.Ambarus@microchip.com";
  x-conformance=spf_only; x-record-type="v=spf1";
  x-record-text="v=spf1 mx a:ushub1.microchip.com
  a:smtpout.microchip.com a:mx1.microchip.iphmx.com
  a:mx2.microchip.iphmx.com include:servers.mcsv.net
  include:mktomail.com include:spf.protection.outlook.com ~all"
Received-SPF: None (esa5.microchip.iphmx.com: no sender
  authenticity information available from domain of
  postmaster@email.microchip.com) identity=helo;
  client-ip=198.175.253.82; receiver=esa5.microchip.iphmx.com;
  envelope-from="Tudor.Ambarus@microchip.com";
  x-sender="postmaster@email.microchip.com";
  x-conformance=spf_only
IronPort-SDR: c+lnhLMbdLj76S8e0GzQcR1cd8cc8qddTQIXo30HzhtSFNeIMWSWtLGaNg8UwC+3WtVj7XVk1T
 GSclZ5yNAngROEeg8JP6s8BqM5GNWHC/4zPepCmvU04OgqVsOgzjjdmOYzekAe9k8ITM7xarMp
 j3nDuevxyIsUD615SRSo2NJqvd3wtcBX9q2IhU4FH2O1HRcJCPx+DAX6z1iIesFvzum+Toieb7
 lKRIBJwSg/oVLVKLsPG+3KTC5A9Uyl59exSBHM1ysCoxLWeFpgVRzfiTkTA2GZiHothsRSzqU/
 MbY=
From:   <Tudor.Ambarus@microchip.com>
To:     <boris.brezillon@collabora.com>, <marek.vasut@gmail.com>,
        <vigneshr@ti.com>
CC:     <dwmw2@infradead.org>, <computersforpeace@gmail.com>,
        <miquel.raynal@bootlin.com>, <richard@nod.at>,
        <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
        <boris.brezillon@bootlin.com>, <Tudor.Ambarus@microchip.com>
Subject: [PATCH 2/6] mtd: spi-nor: Add spansion_post_sfdp_fixups()
Thread-Topic: [PATCH 2/6] mtd: spi-nor: Add spansion_post_sfdp_fixups()
Thread-Index: AQHVR4AIVmwq4cVSO06zdYjm0Oz0Gg==
Date:   Wed, 31 Jul 2019 09:12:10 +0000
Message-ID: <20190731091145.27374-3-tudor.ambarus@microchip.com>
References: <20190731091145.27374-1-tudor.ambarus@microchip.com>
In-Reply-To: <20190731091145.27374-1-tudor.ambarus@microchip.com>
Accept-Language: en-US
Content-Language: en-US
x-ms-exchange-messagesentrepresentingtype: 1
x-mailer: git-send-email 2.9.5
x-originating-ip: [94.177.32.154]
x-ms-publictraffictype: Email
x-ms-office365-filtering-correlation-id: 44a35977-62a9-4212-1c5a-08d715972b08
x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(2017052603328)(7193020);SRVR:MN2PR11MB4414;
x-ms-traffictypediagnostic: MN2PR11MB4414:
x-microsoft-antispam-prvs: <MN2PR11MB4414B5E8F1D73FD3414454E1F0DF0@MN2PR11MB4414.namprd11.prod.outlook.com>
x-ms-oob-tlc-oobclassifiers: OLM:4303;
x-forefront-prvs: 011579F31F
x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(366004)(136003)(396003)(39860400002)(376002)(346002)(199004)(189003)(14454004)(26005)(81166006)(6116002)(50226002)(76176011)(5660300002)(66066001)(2501003)(6512007)(25786009)(486006)(102836004)(107886003)(2201001)(110136005)(305945005)(3846002)(7736002)(68736007)(53936002)(6486002)(478600001)(86362001)(71200400001)(71190400001)(186003)(476003)(256004)(8936002)(6436002)(7416002)(386003)(52116002)(54906003)(316002)(66946007)(81156014)(11346002)(2616005)(2906002)(64756008)(4326008)(446003)(99286004)(36756003)(66556008)(8676002)(66476007)(66446008)(1076003)(6506007);DIR:OUT;SFP:1101;SCL:1;SRVR:MN2PR11MB4414;H:MN2PR11MB4448.namprd11.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1;
received-spf: None (protection.outlook.com: microchip.com does not designate
 permitted sender hosts)
x-ms-exchange-senderadcheck: 1
x-microsoft-antispam-message-info: goMPajPWxJdlPn0k4FmEIEzG6Ta0BhXEs2kxIIbwyrBpCM/BozlJwBwLX/nGh8uKJBlFwdyrd8MIclOn9Lmuoh62djruayZrsMUutsMj/Fq3RyMxvgdyz0fbBxmSOIJ2q2CtpMPUkhXtTTSqY8FMCO5bB8ZWMRM7ScVFkLu3YZB0eIBUKCRjieA5I7ALk8IeDtHoiP15xXzGF0UDVmbxveSG+GPskgc1DjNKMyPK4FL8gd4DJdqFHS4G6echHw7rXq8y7XDmdqqYIgO6frRoQQ1HkhCG1MNs6u82Bgp5cNAI8LRdjPftRAH24MQnQ4EK/iSljwzvxCdzUxQg9QbRa61wvsxlbmwO3q8oBUjc05+CdrzrIN5JUHy1OkWkqJv9tCyjvwH+rw6M/U5I0KHrUBsjYO934lZi4tumEI65PI0=
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-MS-Exchange-CrossTenant-Network-Message-Id: 44a35977-62a9-4212-1c5a-08d715972b08
X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Jul 2019 09:12:10.3712
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: tudor.ambarus@microchip.com
X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4414
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

From: Boris Brezillon <boris.brezillon@bootlin.com>

Add a spansion_post_sfdp_fixups() function to fix the erase opcode,
erase sector size and set the SNOR_F_4B_OPCODES flag.
This way, all spansion related quirks are placed in the
spansion_post_sfdp_fixups() function.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
 drivers/mtd/spi-nor/spi-nor.c | 44 +++++++++++++++++++++++++++++----------=
----
 1 file changed, 30 insertions(+), 14 deletions(-)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 2c2d13060427..30f9d524e72f 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -737,18 +737,6 @@ static u8 spi_nor_convert_3to4_erase(u8 opcode)
=20
 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor)
 {
-	/* Do some manufacturer fixups first */
-	switch (JEDEC_MFR(nor->info)) {
-	case SNOR_MFR_SPANSION:
-		/* No small sector erase for 4-byte command set */
-		nor->erase_opcode =3D SPINOR_OP_SE;
-		nor->mtd.erasesize =3D nor->info->sector_size;
-		break;
-
-	default:
-		break;
-	}
-
 	nor->read_opcode =3D spi_nor_convert_3to4_read(nor->read_opcode);
 	nor->program_opcode =3D spi_nor_convert_3to4_program(nor->program_opcode)=
;
 	nor->erase_opcode =3D spi_nor_convert_3to4_erase(nor->erase_opcode);
@@ -4451,9 +4439,38 @@ static void spi_nor_default_init_params(struct spi_n=
or *nor,
 	spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
 }
=20
+static void spansion_post_sfdp_fixups(struct spi_nor *nor)
+{
+	struct mtd_info *mtd =3D &nor->mtd;
+
+	if (mtd->size <=3D SZ_16M)
+		return;
+
+	nor->flags |=3D SNOR_F_4B_OPCODES;
+	/* No small sector erase for 4-byte command set */
+	nor->erase_opcode =3D SPINOR_OP_SE;
+	nor->mtd.erasesize =3D nor->info->sector_size;
+}
+
+static void
+spi_nor_manufacturer_post_sfdp_fixups(struct spi_nor *nor,
+				      struct spi_nor_flash_parameter *params)
+{
+	switch (JEDEC_MFR(nor->info)) {
+	case SNOR_MFR_SPANSION:
+		spansion_post_sfdp_fixups(nor);
+		break;
+
+	default:
+		break;
+	}
+}
+
 static void spi_nor_post_sfdp_fixups(struct spi_nor *nor,
 				     struct spi_nor_flash_parameter *params)
 {
+	spi_nor_manufacturer_post_sfdp_fixups(nor, params);
+
 	if (nor->info->fixups && nor->info->fixups->post_sfdp)
 		return nor->info->fixups->post_sfdp(nor, params);
 }
@@ -4934,8 +4951,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *nam=
e,
 		nor->addr_width =3D 3;
 	}
=20
-	if (info->flags & SPI_NOR_4B_OPCODES ||
-	    (JEDEC_MFR(info) =3D=3D SNOR_MFR_SPANSION && mtd->size > SZ_16M))
+	if (info->flags & SPI_NOR_4B_OPCODES)
 		nor->flags |=3D SNOR_F_4B_OPCODES;
=20
 	if (nor->addr_width =3D=3D 4 && nor->flags & SNOR_F_4B_OPCODES &&
--=20
2.9.5