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[209.132.180.67]) by mx.google.com with ESMTP id gn3si28479382plb.321.2019.07.31.06.00.39; Wed, 31 Jul 2019 06:00:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=dmWnxkSG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387911AbfGaM4B (ORCPT + 99 others); Wed, 31 Jul 2019 08:56:01 -0400 Received: from mail-lj1-f195.google.com ([209.85.208.195]:37724 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727124AbfGaM4B (ORCPT ); Wed, 31 Jul 2019 08:56:01 -0400 Received: by mail-lj1-f195.google.com with SMTP id z28so11254673ljn.4; Wed, 31 Jul 2019 05:55:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ibb9l9pCzIPRO+qO4A9wjd4O5BSt2O3HIIkOx8g91QE=; b=dmWnxkSGqzJLdXtRSEMnp2346Q5fNymYmV9Q0cYScy4XLd+85hWOnQNs75lW0PNdwi s+cUZbR31z+McMivRqz/ET13p8j7d13H8ixyBqYdGa01zT7PikehyrI8kfDVPwYS9GZ/ zFYiAbkT8SEDQlepklQsZJlRWxVOuLPB7aeZRY6sJxRIzVWQ7zcOtuyLdPKG3zUh5RlI 0oHbwEACO5U76xqu+E+N3nQGmLmWb6O01Gt+vggt6F6esPtXtzRZImt6fDQjjfjF62J1 6jJc7IZ/vQE8pseqlqw2VdpZc531GTaaqylI1C2FXgwhnUbssJN4Uo7PRIKmetfxruYE /qsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ibb9l9pCzIPRO+qO4A9wjd4O5BSt2O3HIIkOx8g91QE=; b=ZaPzxSs2b5LTnk8cPbJS1quD7HJ0gk9a2mm+dNi5r6p8p8GC2pBPrHeSaoNFVAr55W u/0kCy3W4B6n6PXQ/aHllwOIl49PLXZgS0E/bUy4o33ByDewXWOVy5Ufz7Ql1zS1vrFT nEu7k9hbD9IdLgQmPs+62TDW32rIS6VNnirLxbklG2Fpti2ckc1YwKtrhWw147h7ZXjL e8AGZiLIItyK6azyNfSQcNk8MPOwNwZsfmxW9xOcJ20Joagzk9NANkHb2WEFk2HOCtVb RPtrUPq0cGA7unVtDhtnVcc0xKmm+6ROO+Fjr8vivB+BRvm2VzO2gypts88OCXAiZFNV 0R3Q== X-Gm-Message-State: APjAAAWLHPDli1mBZqXdqYelsgb6V1acuv4ptux80tQilxrFm1fdPIfv YzErF+UASpNgb+5aGhHvT8a0I2mZ0WxlwhfGPAWNqB+y X-Received: by 2002:a2e:4e12:: with SMTP id c18mr14146346ljb.211.1564577759040; Wed, 31 Jul 2019 05:55:59 -0700 (PDT) MIME-Version: 1.0 References: <20190731123750.25670-1-philippe.schenker@toradex.com> <20190731123750.25670-8-philippe.schenker@toradex.com> In-Reply-To: <20190731123750.25670-8-philippe.schenker@toradex.com> From: Fabio Estevam Date: Wed, 31 Jul 2019 09:56:05 -0300 Message-ID: Subject: Re: [PATCH v2 07/20] ARM: dts: imx7-colibri: fix 1.8V/UHS support To: Philippe Schenker Cc: Marcel Ziswiler , Max Krummenacher , "stefan@agner.ch" , "devicetree@vger.kernel.org" , Rob Herring , Shawn Guo , Mark Rutland , =?UTF-8?B?TWljaGFsIFZva8OhxI0=?= , Stefan Agner , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Pengutronix Kernel Team , NXP Linux Team , Sascha Hauer Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jul 31, 2019 at 9:38 AM Philippe Schenker wrote: > > From: Stefan Agner > > Add pinmuxing and do not specify voltage restrictions in the > module level device tree. It would be nice to explain the reason for doing this. > Signed-off-by: Stefan Agner > Signed-off-by: Philippe Schenker > --- > > Changes in v2: None > > arch/arm/boot/dts/imx7-colibri.dtsi | 23 ++++++++++++++++++++++- > 1 file changed, 22 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi > index 16d1a1ed1aff..67f5e0c87fdc 100644 > --- a/arch/arm/boot/dts/imx7-colibri.dtsi > +++ b/arch/arm/boot/dts/imx7-colibri.dtsi > @@ -326,7 +326,6 @@ > &usdhc1 { > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; > - no-1-8-v; > cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; > disable-wp; > vqmmc-supply = <®_LDO2>; > @@ -671,6 +670,28 @@ > >; > }; > > + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { > + fsl,pins = < > + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a > + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a > + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a > + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a > + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a > + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a > + >; > + }; > + > + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { > + fsl,pins = < > + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b > + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b > + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b > + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b > + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b > + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b > + >; > + }; You add the entries for 100MHz and 200MHz, but I don't see them being referenced anywhere.