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Subject: Re: [PATCH v7 11/20] cpufreq: tegra124: Add suspend and resume
 support
To:     Dmitry Osipenko <digetx@gmail.com>, <thierry.reding@gmail.com>,
        <jonathanh@nvidia.com>, <tglx@linutronix.de>,
        <jason@lakedaemon.net>, <marc.zyngier@arm.com>,
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From:   Sowjanya Komatineni <skomatineni@nvidia.com>
Message-ID: <99c76e3a-6f7b-ef9a-2fd7-03744da650c4@nvidia.com>
Date:   Wed, 31 Jul 2019 14:05:49 -0700
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On 7/31/19 4:14 AM, Dmitry Osipenko wrote:
> 31.07.2019 13:23, Dmitry Osipenko =D0=BF=D0=B8=D1=88=D0=B5=D1=82:
>> 31.07.2019 3:20, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82:
>>> This patch adds suspend and resume pm ops for cpufreq driver.
>>>
>>> PLLP is the safe clock source for CPU during system suspend and
>>> resume as PLLP rate is below the CPU Fmax at Vmin.
>>>
>>> CPUFreq driver suspend switches the CPU clock source to PLLP and
>>> disables the DFLL clock.
>>>
>>> During system resume, warmboot code powers up the CPU with PLLP
>>> clock source. So CPUFreq driver resume enabled DFLL clock and
>>> switches CPU back to DFLL clock source.
>>>
>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>> ---
>>>   drivers/cpufreq/tegra124-cpufreq.c | 60 +++++++++++++++++++++++++++++=
+++++++++
>>>   1 file changed, 60 insertions(+)
>>>
>>> diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra=
124-cpufreq.c
>>> index 4f0c637b3b49..e979a3370988 100644
>>> --- a/drivers/cpufreq/tegra124-cpufreq.c
>>> +++ b/drivers/cpufreq/tegra124-cpufreq.c
>>> @@ -6,6 +6,7 @@
>>>   #define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
>>>  =20
>>>   #include <linux/clk.h>
>>> +#include <linux/cpufreq.h>
>>>   #include <linux/err.h>
>>>   #include <linux/init.h>
>>>   #include <linux/kernel.h>
>>> @@ -128,8 +129,67 @@ static int tegra124_cpufreq_probe(struct platform_=
device *pdev)
>>>   	return ret;
>>>   }
>>>  =20
>>> +static int __maybe_unused tegra124_cpufreq_suspend(struct device *dev)
>>> +{
>>> +	struct tegra124_cpufreq_priv *priv =3D dev_get_drvdata(dev);
>>> +	int err;
>>> +
>>> +	/*
>>> +	 * PLLP rate 408Mhz is below the CPU Fmax at Vmin and is safe to
>>> +	 * use during suspend and resume. So, switch the CPU clock source
>>> +	 * to PLLP and disable DFLL.
>>> +	 */
>>> +	err =3D clk_set_parent(priv->cpu_clk, priv->pllp_clk);
>>> +	if (err < 0) {
>>> +		dev_err(dev, "failed to reparent to PLLP: %d\n", err);
>>> +		return err;
>>> +	}
>>> +
>>> +	/* disable DFLL clock */
>>> +	clk_disable_unprepare(priv->dfll_clk);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static int __maybe_unused tegra124_cpufreq_resume(struct device *dev)
>>> +{
>>> +	struct tegra124_cpufreq_priv *priv =3D dev_get_drvdata(dev);
>>> +	int err;
>>> +
>>> +	/*
>>> +	 * Warmboot code powers up the CPU with PLLP clock source.
>>> +	 * Enable DFLL clock and switch CPU clock source back to DFLL.
>>> +	 */
>>> +	err =3D clk_prepare_enable(priv->dfll_clk);
>>> +	if (err < 0) {
>>> +		dev_err(dev, "failed to enable DFLL clock for CPU: %d\n", err);
>>> +		goto disable_cpufreq;
>>> +	}
>>> +
>>> +	err =3D clk_set_parent(priv->cpu_clk, priv->dfll_clk);
>>> +	if (err < 0) {
>>> +		dev_err(dev, "failed to reparent to DFLL clock: %d\n", err);
>>> +		goto disable_dfll;
>>> +	}
>>> +
>>> +	return 0;
>>> +
>>> +disable_dfll:
>>> +	clk_disable_unprepare(priv->dfll_clk);
>>> +disable_cpufreq:
>>> +	disable_cpufreq();
>>> +
>>> +	return err;
>>> +}
>>> +
>>> +static const struct dev_pm_ops tegra124_cpufreq_pm_ops =3D {
>>> +	SET_SYSTEM_SLEEP_PM_OPS(tegra124_cpufreq_suspend,
>>> +				tegra124_cpufreq_resume)
>>> +};
>>> +
>>>   static struct platform_driver tegra124_cpufreq_platdrv =3D {
>>>   	.driver.name	=3D "cpufreq-tegra124",
>>> +	.driver.pm	=3D &tegra124_cpufreq_pm_ops,
>>>   	.probe		=3D tegra124_cpufreq_probe,
>>>   };
>>>  =20
>>>
>> Looks good,
>>
>> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
>>
> BTW, you should also CC the CPUFreq maintainers because this patch can't
> be applied without theirs ACK.
MIssed them. Will resend v7 series with CPUFreq maintainers...