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Thu, 1 Aug 2019 04:47:13 +0000 From: Naga Sureshkumar Relli To: Boris Brezillon CC: "Tudor.Ambarus@microchip.com" , "marek.vasut@gmail.com" , "vigneshr@ti.com" , "richard@nod.at" , "linux-kernel@vger.kernel.org" , "linux-mtd@lists.infradead.org" , "miquel.raynal@bootlin.com" , "computersforpeace@gmail.com" , "dwmw2@infradead.org" Subject: RE: [PATCH 5/6] mtd: spi-nor: Add s3an_post_sfdp_fixups() Thread-Topic: [PATCH 5/6] mtd: spi-nor: Add s3an_post_sfdp_fixups() Thread-Index: AQHVR4AuPtwOhxyzBUKoXu06OueqLabkpU9AgAAFXgCAAQ6NsA== Date: Thu, 1 Aug 2019 04:47:12 +0000 Message-ID: References: <20190731091145.27374-1-tudor.ambarus@microchip.com> <20190731091145.27374-6-tudor.ambarus@microchip.com> <20190731143822.79fa7c82@collabora.com> In-Reply-To: <20190731143822.79fa7c82@collabora.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=nagasure@xilinx.com; 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received-spf: None (protection.outlook.com: xilinx.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: b6RO5zC6C2ycFOoTydBNWmRgBuykmuEJ7copsyKaoB4QsqCVKr2L0dByL7CBMonChSaK4Zuo5PWl5YjxHlmLwid5lRCINw9qOML0VK9tYiXDg2wpY1N+RNVJosLvSdNtTond2N51tiNaC7e2mGnDGBd9CRtH0PTUIcKmQe5oYrLLz0geClXWTUA+/Scl4JaxRxAZgruYZ+fwOenRMGK0/ZPPbul33vxn3KxW1JdcDM1gxyNyHoDtvM+/YeFWeNO3iPu9LgORHNbOroqeBP653dd0sBQUlA9BGA4M0qjjaK/9o879+BbuOmHoHXfrlHkU+ukv6/Bgs+6Gl3gmoB9HZDCYnOdjJaBRzQRS65P58i8THRMWur0pA/U7Iav9isX3A8ZNGQ7WheZzf6SWsq1kCUU78V4sBaF700CzsAzxFAM= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-Network-Message-Id: 256e44c3-e3e6-40b0-ef49-08d7163b5209 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Aug 2019 04:47:13.0079 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: nagasure@xilinx.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR02MB7102 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Boris Brezillon > Sent: Wednesday, July 31, 2019 6:08 PM > To: Naga Sureshkumar Relli > Cc: Tudor.Ambarus@microchip.com; marek.vasut@gmail.com; vigneshr@ti.com; > richard@nod.at; linux-kernel@vger.kernel.org; linux-mtd@lists.infradead.o= rg; > miquel.raynal@bootlin.com; computersforpeace@gmail.com; dwmw2@infradead.o= rg > Subject: Re: [PATCH 5/6] mtd: spi-nor: Add s3an_post_sfdp_fixups() >=20 > On Wed, 31 Jul 2019 12:31:19 +0000 > Naga Sureshkumar Relli wrote: >=20 > > Hi Tudor, > > > > Thanks for the updates. With these kind of updates, we can add Vendor > > specific Code easily, like Xilinx Dual parallel and stacked modes. > > In these configurations we need to tweak the nor parameters like page_s= ize, sectors etc. > > So with the help of these patches. we can easily update these parameter= s. >=20 > Absolutely not. This is just a solution to recover from broken SFDP table= s. Ok. Thanks, Naga Sureshkumar Relli