Received: by 2002:a25:ad19:0:0:0:0:0 with SMTP id y25csp7059446ybi; Thu, 1 Aug 2019 02:35:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqxjf7ZJPepEaOvlFeOoPO5nGYDShL7jojNvDV5uHPtIcfyv0Wc3S1Ic5dHfmw5Kd5Tg/6n2 X-Received: by 2002:a17:90a:a116:: with SMTP id s22mr7530060pjp.47.1564652146641; Thu, 01 Aug 2019 02:35:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564652146; cv=none; d=google.com; s=arc-20160816; b=08vpGr03qstcv3ASFL/uvN0PGOPtABSQKP6+WPgJWcNWsl8DoF1oTtvANEEMYEGG4b ZQW1UePEZiY0m+NMZNBlR/ZkZem7aLrvcd7sLfuq7my4yfsYB2j26K6ZNd1seEtf60cM ou5TRTv2Wvemz4p32Cpa+UvLuhecwVFfeD0ocHU/+0dQJiQoZojdm4874Nk0rB82SK7I Tb82TjuEe9sSJR+QZRMWL5aemZ/iUtBuD4LetBif/z30SgRJ0vWvsUKfjwVGbdGs2Oo+ zfzqJSfcR0rFacnw4p++A3a44VnvflgRwDR8ccqUgS8eTUzgu9xfii36WMawli/1It30 0Oyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from; bh=UE5VNFJty4Y75B0uAczzZqCwIoetO/aN2lM7/BApUtI=; b=crkGMUKHGAN9GiCawAnPJnhydV7eCDtc+V6aAesZFlbQYyvBq4CdxmzuoowRQvGc0g p1eqyDtioezaGpbrENGauIhb6/ot43LQV9G7nL2BCnOq7jHxyf2ySF4htNEgl/C5Kh8w wEWGGxCUaWKE6O6ry9Ie191A9EfrN3YGrJu4/ZXHeXGHG+vNJIHFpvzE0Bf0Zw9v4GgW TLL0+jxmoKp88zPo6FqauaV8uUyow570hgA+IDSEseCesGtqUQVyBu4d6ITMoRRC8vSS wCAgsfRxonGnS3NigXE+7iQM2+v+4ZaxxjcwznhVRYnvkw0alPcFD/fvt+xkRe3nRmIc EVZg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b93si32694642plb.11.2019.08.01.02.35.30; Thu, 01 Aug 2019 02:35:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731132AbfHAIVH (ORCPT + 99 others); Thu, 1 Aug 2019 04:21:07 -0400 Received: from honk.sigxcpu.org ([24.134.29.49]:43924 "EHLO honk.sigxcpu.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731106AbfHAIVE (ORCPT ); Thu, 1 Aug 2019 04:21:04 -0400 Received: from localhost (localhost [127.0.0.1]) by honk.sigxcpu.org (Postfix) with ESMTP id E9E22FB02; Thu, 1 Aug 2019 10:21:01 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at honk.sigxcpu.org Received: from honk.sigxcpu.org ([127.0.0.1]) by localhost (honk.sigxcpu.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7cL5DYKqFopF; Thu, 1 Aug 2019 10:20:59 +0200 (CEST) Received: by bogon.sigxcpu.org (Postfix, from userid 1000) id 4B5E246DE9; Thu, 1 Aug 2019 10:20:59 +0200 (CEST) From: =?UTF-8?q?Guido=20G=C3=BCnther?= To: Philipp Zabel , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/1] dt-bindings: reset: Fix typo in imx8mq resets Date: Thu, 1 Aug 2019 10:20:59 +0200 Message-Id: <660b4fb6ab9acec05aa5fde323d878e04e3d1f64.1564647612.git.agx@sigxcpu.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some of the mipi dsi resets were called IMX8MQ_RESET_MIPI_DIS__ instead of IMX8MQ_RESET_MIPI_DSI__ Since they're DSI related this looks like a typo. This fixes the only in tree user as well to not break bisecting. Signed-off-by: Guido Günther --- drivers/reset/reset-imx7.c | 12 ++++++------ include/dt-bindings/reset/imx8mq-reset.h | 6 +++--- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c index 3ecd770f910b..1443a55a0c29 100644 --- a/drivers/reset/reset-imx7.c +++ b/drivers/reset/reset-imx7.c @@ -169,9 +169,9 @@ static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = { [IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) }, [IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) }, [IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) }, - [IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) }, - [IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) }, - [IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) }, + [IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) }, + [IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) }, + [IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) }, [IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) }, [IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, @@ -220,9 +220,9 @@ static int imx8mq_reset_set(struct reset_controller_dev *rcdev, case IMX8MQ_RESET_PCIE_CTRL_APPS_EN: case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */ - case IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N: /* fallthrough */ - case IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N: /* fallthrough */ - case IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N: /* fallthrough */ + case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N: /* fallthrough */ + case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N: /* fallthrough */ + case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N: /* fallthrough */ case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */ case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */ value = assert ? 0 : bit; diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h index 57c592498aa0..bfa41b0e24f6 100644 --- a/include/dt-bindings/reset/imx8mq-reset.h +++ b/include/dt-bindings/reset/imx8mq-reset.h @@ -31,9 +31,9 @@ #define IMX8MQ_RESET_OTG2_PHY_RESET 20 #define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 #define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 -#define IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N 23 -#define IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N 24 -#define IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N 25 +#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 +#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 +#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 #define IMX8MQ_RESET_PCIEPHY 26 #define IMX8MQ_RESET_PCIEPHY_PERST 27 #define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 -- 2.20.1