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Subject: Re: [PATCH v2] MIPS: Ingenic: Fix bugs when detecting X1000's
 parameters.
To:     Paul Burton <paul.burton@mips.com>
References: <1564498510-3751-1-git-send-email-zhouyanjie@zoho.com>
 <1564547943-27505-1-git-send-email-zhouyanjie@zoho.com>
 <1564547943-27505-2-git-send-email-zhouyanjie@zoho.com>
 <20190731203430.2wst6pivwxnmtt74@pburton-laptop>
Cc:     "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "ralf@linux-mips.org" <ralf@linux-mips.org>,
        "paul@crapouillou.net" <paul@crapouillou.net>,
        "jhogan@kernel.org" <jhogan@kernel.org>,
        "malat@debian.org" <malat@debian.org>,
        "chenhc@lemote.com" <chenhc@lemote.com>,
        "tglx@linutronix.de" <tglx@linutronix.de>,
        "allison@lohutok.net" <allison@lohutok.net>,
        "syq@debian.org" <syq@debian.org>,
        "jiaxun.yang@flygoat.com" <jiaxun.yang@flygoat.com>
From:   Zhou Yanjie <zhouyanjie@zoho.com>
Message-ID: <5D42C51E.1090906@zoho.com>
Date:   Thu, 1 Aug 2019 18:55:26 +0800
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Hi Paul,

On 2019=E5=B9=B408=E6=9C=8801=E6=97=A5 04:34, Paul Burton wrote:
> Hi Zhou,
>
> On Wed, Jul 31, 2019 at 12:39:03PM +0800, Zhou Yanjie wrote:
>> 1.fix bugs when detecting L2 cache sets value.
>> 2.fix bugs when detecting L2 cache ways value.
>> 3.fix bugs when calculate bogoMips and loops_per_jiffy.
> This should be split into 2 patches - one that fixes the L2 cache
> detection problems, and possibly one that fixes the bogomips/lpj issue.
Thanks for your advice. I have split it in v3.
>
>> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
>> ---
>>   arch/mips/include/asm/mipsregs.h |  1 +
>>   arch/mips/kernel/cpu-probe.c     |  7 +++++++
>>   arch/mips/mm/sc-mips.c           | 18 +++++++++++++++---
>>   3 files changed, 23 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mi=
psregs.h
>> index 1e6966e..01e0fcb 100644
>> --- a/arch/mips/include/asm/mipsregs.h
>> +++ b/arch/mips/include/asm/mipsregs.h
>> @@ -2813,6 +2813,7 @@ __BUILD_SET_C0(status)
>>   __BUILD_SET_C0(cause)
>>   __BUILD_SET_C0(config)
>>   __BUILD_SET_C0(config5)
>> +__BUILD_SET_C0(config7)
>>   __BUILD_SET_C0(intcontrol)
>>   __BUILD_SET_C0(intctl)
>>   __BUILD_SET_C0(srsmap)
>> diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
>> index eb527a1..547c9a0 100644
>> --- a/arch/mips/kernel/cpu-probe.c
>> +++ b/arch/mips/kernel/cpu-probe.c
>> @@ -1964,6 +1964,13 @@ static inline void cpu_probe_ingenic(struct cpuin=
fo_mips *c, unsigned int cpu)
>>   =09=09c->cputype =3D CPU_XBURST;
>>   =09=09c->writecombine =3D _CACHE_UNCACHED_ACCELERATED;
>>   =09=09__cpu_name[cpu] =3D "Ingenic XBurst";
>> +=09=09/*
>> +=09=09 * config7 bit 4 is used to control a low-power mode in
>> +=09=09 * XBurst architecture. This mode may cause errors in the
>> +=09=09 * calculation of bogomips and loops_per_jiffy, set config7
>> +=09=09 * bit 4 to disable this feature to prevent that.
>> +=09=09 */
>> +=09=09set_c0_config7(BIT(4));
> I happen to know what this bit does - see this old patch for an
> explanation:
>
>    https://github.com/paulburton/linux/commit/0d72377bd615d00e99733adc0d3=
7e6a2373fcde7
>
> In short it disables a loop optimization in the CPU that is supposed to
> special case loops & prevent them from relying upon the BTB.
> Unfortunately that loop optimization negatively affects short loops,
> such as in __delay(), and Ingenic's vendor kernels have generally set
> this bit to disable it.
>
> Note though that bogomips is bogus, so changing the bogomips value is
> really not good justification for the patch at all (which is why I've so
> far not bothered upstreaming the patch linked above). The best
> justification I can think of is that Ingenic set the bit in their
> downstream kernels, which presumably means it's beneficial overall (or
> just that someone cares too much about bogomips).
>
> In any case, one thing I don't know for sure is which CPU versions are
> affected. I don't believe this affected older devices like the JZ4740,
> and my copy of the XBurst1 CPU Core Programming Manual documents the bit
> as reserved. Given that you're seeing the X1000 is affected, and I know
> the JZ4780 is affected, that covers at least 2 different PRIDs so we
> can't just check for that.
>
> Hopefully writing to the bit is just a no-op on older systems if it is
> actually reserved, but it'd be great if we could test that.
>
> At the very least we should define the bit in asm/mipsregs.h & properly
> document what it does - using BIT(4) here may be a little nicer than
> (1<<4), but it's still just a magic number. I don't mind if you want to
> fix your patch to do that, or one of us can resurrect mine which has
> that information already.
I have verified the Ingenic's CPU department. According to their reply,
all XBurst1 cores support this feature. Therefore, it is safe to turn off i=
t
in XBurst1.

However, the hardware that I can use normally is JZ4760 and later, so
the JZ4730/JZ4740/JZ4750 has not been tested. So for safe we can also
turn off this feature only in JZ4760 and later if necessary. Wait for your
comments and if necessary I will change it in v4.
>>   =09=09break;
>>   =09default:
>>   =09=09panic("Unknown Ingenic Processor ID!");
>> diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
>> index 9385ddb..ed953d4 100644
>> --- a/arch/mips/mm/sc-mips.c
>> +++ b/arch/mips/mm/sc-mips.c
>> @@ -215,6 +215,14 @@ static inline int __init mips_sc_probe(void)
>>   =09else
>>   =09=09return 0;
>>  =20
>> +=09/*
>> +=09 * According to config2 it would be 512-sets, but that is contradict=
ed
>> +=09 * by all documentation.
>> +=09 */
>> +=09if (current_cpu_type() =3D=3D CPU_XBURST &&
>> +=09=09=09=09mips_machtype =3D=3D MACH_INGENIC_X1000)
>> +=09=09c->scache.sets =3D 256;
>> +
>>   =09tmp =3D (config2 >> 0) & 0x0f;
>>   =09if (tmp <=3D 7)
>>   =09=09c->scache.ways =3D tmp + 1;
>> @@ -225,9 +233,13 @@ static inline int __init mips_sc_probe(void)
>>   =09 * According to config2 it would be 5-ways, but that is contradicte=
d
>>   =09 * by all documentation.
>>   =09 */
>> -=09if (current_cpu_type() =3D=3D CPU_XBURST &&
>> -=09=09=09=09mips_machtype =3D=3D MACH_INGENIC_JZ4770)
>> -=09=09c->scache.ways =3D 4;
>> +=09if (current_cpu_type() =3D=3D CPU_XBURST) {
>> +=09=09switch (mips_machtype) {
>> +=09=09case MACH_INGENIC_JZ4770:
>> +=09=09case MACH_INGENIC_X1000:
>> +=09=09=09c->scache.ways =3D 4;
>> +=09=09}
>> +=09}
>>  =20
>>   =09c->scache.waysize =3D c->scache.sets * c->scache.linesz;
>>   =09c->scache.waybit =3D __ffs(c->scache.waysize);
> Given that we need to fix up both sets & ways, I think this would be
> cleaner if both were done in the switch statement here after we've read
> the values from Config2. ie. something like:
>
> =09if (current_cpu_type() =3D=3D CPU_XBURST) {
> =09=09switch (mips_machtype) {
> =09=09case MACH_INGENIC_JZ4770:
> =09=09=09c->scache.ways =3D 4;
> =09=09=09break;
>
> =09=09case MACH_INGENIC_X1000:
> =09=09=09c->scache.sets =3D 256;
> =09=09=09c->scache.ways =3D 4;
> =09=09=09break;
> =09=09}
> =09}
>
> With appropriate comments added for each machine/SoC.

Thanks for you advice. I have change it in v3.
>
> Thanks,
>      Paul