Subject: Re: [discuss] [patch] x86_64:  align and pad x86_64 GDT on page
	boundary
From: Rohit Seth <rohit.seth@intel.com>
To: Ravikiran G Thirumalai <kiran@scalex86.org>
Cc: Andi Kleen <ak@suse.de>, Andrew Morton <akpm@osdl.org>,
       linux-kernel@vger.kernel.org, discuss@x86-64.org, zach@vmware.com,
       shai@scalex86.org, nippung@calsoftinc.com
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Organization: Intel 
Date: Fri, 09 Dec 2005 15:01:27 -0800
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On Fri, 2005-12-09 at 14:19 -0800, Ravikiran G Thirumalai wrote:
> On Fri, Dec 09, 2005 at 12:43:20AM +0100, Andi Kleen wrote:
> >
> > For scalex I think it needs to be page aligned because that is what
> > the effective cacheline size for remote nodes is in their setup. 
> > That would be difficult for kmalloc because it cannot guarantee that
> > alignment nor avoid false sharing. 
> 
> Exactly.
> 

Are you saying remote node will cache a whole page for every byte access
on that page.

> > For the BP case it's ok as 
> > long as the beginning is correctly aligned and the rest 
> > is read-only.
> 
> Just that any writes on the bp GDT will invalidate the idt_table cacheline,
> which is read mostly (as Nippun pointed out).  So could we keep the padding
> as it is for the BP too? 
> 

Do you write into GDT often for this to be an issue.  The reason I'm
asking this because the per-cpu IDTs that Andi refered in the future.
If we are really not using too many bytes in GDT then rest of the page
can be used for IDT and such mostly RO data.

-rohit

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