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Date:   Fri, 2 Aug 2019 18:33:28 +0200
From:   Peter Zijlstra <peterz@infradead.org>
To:     "Lendacky, Thomas" <Thomas.Lendacky@amd.com>
Cc:     Thomas Gleixner <tglx@linutronix.de>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "x86@kernel.org" <x86@kernel.org>, Ingo Molnar <mingo@redhat.com>,
        Borislav Petkov <bp@alien8.de>,
        Arnaldo Carvalho de Melo <acme@kernel.org>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Namhyung Kim <namhyung@kernel.org>,
        Jiri Olsa <jolsa@redhat.com>,
        Jerry Hoemann <jerry.hoemann@hpe.com>
Subject: Re: [PATCH] perf/x86/amd: Change NMI latency mitigation to use a
 timestamp
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On Fri, Aug 02, 2019 at 06:20:15PM +0200, Peter Zijlstra wrote:
> On Fri, Aug 02, 2019 at 02:33:41PM +0000, Lendacky, Thomas wrote:

> > Talking to the hardware folks, they say setting CR8 is a serializing
> > instruction and has to communicate out to the APIC, so it's better to
> > use CLI/STI.
> 
> Bah; the Intel SDM states: "MOV CR* instructions, except for MOV CR8,
> are serializing instructions", which had given me a little hope.
> 
> At the same time, all these chips still have the APIC TPR field too, so
> much like how the TSC DEADLINE MSR is a hidden APIC write, so too is CR8
> I suppose :-(
> 
> I'll still finish the patches I started, just to see what it would look
> like.

Another 'fun' issue I ran into while doing these patches; STI has a 1
instruction shadow, which we rely on, MOV CR8 does not. So things like:

native_safe_halt:
	sti
	hlt

turn into:

native_safe_halt:
	cli
	movl $0, %rax
	movq %rax, %cr8
	sti
	hlt