Received: by 2002:a25:b794:0:0:0:0:0 with SMTP id n20csp4241791ybh; Tue, 6 Aug 2019 08:28:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqynZteZ9YiC592Mu/Uet1c1q91Ir+DZfpSUFFCWdJVTx76OkZwSw53NPZtCqCoVwDnqpQo8 X-Received: by 2002:a17:90a:cb81:: with SMTP id a1mr3675103pju.81.1565105280229; Tue, 06 Aug 2019 08:28:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565105280; cv=none; d=google.com; s=arc-20160816; b=UpwyQXp7wqlXbZmdOeBhjBUveS5sZLnb1ErT3eNnhrConSSc5TJrsG0WEDyYRvQ6IS Etk4OH4RHGp9OLmaSTcMBXJ9VNmoOSM7+39UYjTB82rb6fyrJlRqy5l2+tHmaO1FaJwp iqanqVK202ODBBBO1SW6VWQNOQNUuoMtXVe4dMkN5APrDo4yqMxz7kreXSfuYq69miqa tz3CtpPIHB5ctt7rOOoKwfOdqF2jg6zkUNVAK1MQhb6XYhvX4zvFnNdpQqHidtGcrMQK se60QskB52o4ahsS2lYOxleQrxHR9zcJBrdCLo2zOja3lhq+BqGK4MbqZqMMuaEy/9+T T8dQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-disposition:mime-version:references:message-id:subject:cc :to:from:date; bh=H5fXiTqQsk126cUZpZh69XTGIq5hlkA7H9dGyLdpP9Y=; b=o/he6jHDssmv/OZvQWDOK8kQr4fVQOy3Xn+LtCUUN4HCTffsCNpO4awtdSwKP6m1iP Na5Nmkv3lGH7960UGqydNM1jdQw5chZoV6l3ITBAAo5bd2UkqSsxhisnodZYfnGyLCHA DoqBjBF4YZHJOFd21Xeu4LUpWEmjIRw86jznp9XSv+qCQC5UsjQvv7/xIrWOno4cwK47 rT9XD8vG5ut/wyk8CEFeFM9QnU+l2LmiW2x1j2MMnSdnvOPetldXvh+w1l+yM6S7hloU IYrsAPfzqxAeO/N1QYgwLoRsWIvMZaCvawvqMy4zfXKWksSlbth1gF0ZbKFRj8by/ypY 0SbA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e30si47848647pfm.78.2019.08.06.08.27.43; Tue, 06 Aug 2019 08:28:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732922AbfHFOfD (ORCPT + 99 others); Tue, 6 Aug 2019 10:35:03 -0400 Received: from foss.arm.com ([217.140.110.172]:34232 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728756AbfHFOfC (ORCPT ); Tue, 6 Aug 2019 10:35:02 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C162B344; Tue, 6 Aug 2019 07:35:01 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BD5F23F706; Tue, 6 Aug 2019 07:34:59 -0700 (PDT) Date: Tue, 6 Aug 2019 15:34:57 +0100 From: Mark Rutland To: Rob Clark Cc: Christoph Hellwig , Rob Clark , dri-devel , Catalin Marinas , Will Deacon , Maarten Lankhorst , Maxime Ripard , Sean Paul , David Airlie , Daniel Vetter , Allison Randal , Greg Kroah-Hartman , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, LKML Subject: Re: [PATCH 1/2] drm: add cache support for arm64 Message-ID: <20190806143457.GF475@lakrids.cambridge.arm.com> References: <20190805211451.20176-1-robdclark@gmail.com> <20190806084821.GA17129@lst.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.11.1+11 (2f07cb52) (2018-12-01) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Aug 06, 2019 at 07:11:41AM -0700, Rob Clark wrote: > On Tue, Aug 6, 2019 at 1:48 AM Christoph Hellwig wrote: > > > > This goes in the wrong direction. drm_cflush_* are a bad API we need to > > get rid of, not add use of it. The reason for that is two-fold: > > > > a) it doesn't address how cache maintaince actually works in most > > platforms. When talking about a cache we three fundamental operations: > > > > 1) write back - this writes the content of the cache back to the > > backing memory > > 2) invalidate - this remove the content of the cache > > 3) write back + invalidate - do both of the above > > Agreed that drm_cflush_* isn't a great API. In this particular case > (IIUC), I need wb+inv so that there aren't dirty cache lines that drop > out to memory later, and so that I don't get a cache hit on > uncached/wc mmap'ing. Is there a cacheable alias lying around (e.g. the linear map), or are these addresses only mapped uncached/wc? If there's a cacheable alias, performing an invalidate isn't sufficient, since a CPU can allocate a new (clean) entry at any point in time (e.g. as a result of prefetching or arbitrary speculation). Thanks, Mark.