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[73.95.159.87]) by smtp.gmail.com with ESMTPSA id t19sm78314934iog.41.2019.08.06.14.37.59 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 06 Aug 2019 14:37:59 -0700 (PDT) Date: Tue, 6 Aug 2019 14:37:58 -0700 (PDT) From: Paul Walmsley X-X-Sender: paulw@viisi.sifive.com To: Atish Patra cc: linux-kernel@vger.kernel.org, Alan Kao , Albert Ou , Anup Patel , Daniel Lezcano , devicetree@vger.kernel.org, Enrico Weigelt , Greg Kroah-Hartman , Johan Hovold , linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Rob Herring , Thomas Gleixner Subject: Re: [PATCH v4 1/4] RISC-V: Remove per cpu clocksource In-Reply-To: <20190803042723.7163-2-atish.patra@wdc.com> Message-ID: References: <20190803042723.7163-1-atish.patra@wdc.com> <20190803042723.7163-2-atish.patra@wdc.com> User-Agent: Alpine 2.21.9999 (DEB 301 2018-08-15) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 2 Aug 2019, Atish Patra wrote: > There is only one clocksource in RISC-V. The boot cpu initializes > that clocksource. No need to keep a percpu data structure. > > Signed-off-by: Atish Patra Thanks, queued for v5.3-rc4. - Paul