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[209.132.180.67]) by mx.google.com with ESMTP id h26si44819280pgl.398.2019.08.06.23.05.47; Tue, 06 Aug 2019 23:06:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727011AbfHGGDT (ORCPT + 99 others); Wed, 7 Aug 2019 02:03:19 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:9357 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726777AbfHGGDS (ORCPT ); Wed, 7 Aug 2019 02:03:18 -0400 X-UUID: 9a2df9b7262d4750a79ae726566ef34a-20190807 X-UUID: 9a2df9b7262d4750a79ae726566ef34a-20190807 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1505431920; Wed, 07 Aug 2019 14:03:08 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33N1.mediatek.inc (172.27.4.75) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 7 Aug 2019 14:03:04 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (172.27.4.253) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 7 Aug 2019 14:03:02 +0800 From: Jitao Shi To: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , , David Airlie , Matthias Brugger CC: Jitao Shi , Thierry Reding , Ajay Kumar , Inki Dae , Rahul Sharma , Sean Paul , Vincent Palatin , Andy Yan , Philipp Zabel , Russell King , , , , , , , Sascha Hauer , , , , , , Subject: [PATCH v5 1/4] dt-bindings: display: mediatek: update dpi supported chips Date: Wed, 7 Aug 2019 14:02:54 +0800 Message-ID: <20190807060257.57007-2-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190807060257.57007-1-jitao.shi@mediatek.com> References: <20190807060257.57007-1-jitao.shi@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-TM-SNTS-SMTP: C69E228641317CEF5F977F938A43637FA6695ED07D1225B291DE2BC80CE66BAA2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add decriptions about supported chips, including MT2701 & MT8173 & mt8183 Signed-off-by: Jitao Shi --- .../bindings/display/mediatek/mediatek,dpi.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt index b6a7e7397b8b..cd6a1469c8b7 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt @@ -7,6 +7,7 @@ output bus. Required properties: - compatible: "mediatek,-dpi" + the supported chips are mt2701 , mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - interrupts: The interrupt signal from the function block. - clocks: device clocks @@ -16,6 +17,11 @@ Required properties: Documentation/devicetree/bindings/graph.txt. This port should be connected to the input port of an attached HDMI or LVDS encoder chip. +Optional properties: +- dpi_pin_mode_swap: Swap the pin mode between dpi mode and gpio mode. +- pinctrl-names: Contain "gpiomode" and "dpimode". +- dpi_dual_edge: Control the RGB 24bit data on 12 pins or 24 pins. + Example: dpi0: dpi@1401d000 { @@ -26,6 +32,11 @@ dpi0: dpi@1401d000 { <&mmsys CLK_MM_DPI_ENGINE>, <&apmixedsys CLK_APMIXED_TVDPLL>; clock-names = "pixel", "engine", "pll"; + dpi_dual_edge; + dpi_pin_mode_swap; + pinctrl-names = "gpiomode", "dpimode"; + pinctrl-0 = <&dpi_pin_gpio>; + pinctrl-1 = <&dpi_pin_func>; port { dpi0_out: endpoint { -- 2.21.0