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Date:   Wed, 07 Aug 2019 09:20:17 -0700 (PDT)
Subject:     Re: [PATCH] riscv: kbuild: add virtual memory system selection
In-Reply-To: <20190807151229.GA16432@infradead.org>
CC:     alex@ghiti.fr, Christoph Hellwig <hch@infradead.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
From:   Palmer Dabbelt <palmer@sifive.com>
To:     Christoph Hellwig <hch@infradead.org>
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On Wed, 07 Aug 2019 08:12:30 PDT (-0700), Christoph Hellwig wrote:
> On Wed, Aug 07, 2019 at 09:04:40AM +0200, Alexandre Ghiti wrote:
>> I took a look at how x86 deals with 5-level page table: it allows to handle
>> 5-level and 4-level at runtime by folding the last page table level (cf
>> Documentation/x86/x86_64/5level-paging.rst). So we might want to be able to
>> do the same and deal with that at runtime.
>
> Yes, following the X86_5LEVEL model is the right thing.

I poked around a bit with this last night, but our paging implemention is super
ugly so it'd be better to clean all that up first.  No idea when I'll have time
to do so...