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[209.132.180.67]) by mx.google.com with ESMTP id m143si52535812pfd.224.2019.08.08.02.58.40; Thu, 08 Aug 2019 02:58:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731588AbfHHJ54 (ORCPT + 99 others); Thu, 8 Aug 2019 05:57:56 -0400 Received: from mga05.intel.com ([192.55.52.43]:50931 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728289AbfHHJ54 (ORCPT ); Thu, 8 Aug 2019 05:57:56 -0400 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Aug 2019 02:57:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,360,1559545200"; d="scan'208";a="193122144" Received: from lahna.fi.intel.com (HELO lahna) ([10.237.72.157]) by fmsmga001.fm.intel.com with SMTP; 08 Aug 2019 02:57:51 -0700 Received: by lahna (sSMTP sendmail emulation); Thu, 08 Aug 2019 12:57:51 +0300 Date: Thu, 8 Aug 2019 12:57:51 +0300 From: 'Mika Westerberg' To: David Laight Cc: 'Yehezkel Bernat' , LKML , Andreas Noever , Michael Jamet , "Rafael J . Wysocki" , Len Brown , Lukas Wunner , Mario Limonciello , Anthony Wong , "linux-acpi@vger.kernel.org" Subject: Re: [PATCH 3/8] thunderbolt: Use 32-bit writes when writing ring producer/consumer Message-ID: <20190808095751.GA2716@lahna.fi.intel.com> References: <20190705095800.43534-1-mika.westerberg@linux.intel.com> <20190705095800.43534-4-mika.westerberg@linux.intel.com> <0f3a47d8133945b181d623ea6e0d53f2@AcuMS.aculab.com> <20190807161359.GT2716@lahna.fi.intel.com> <79616dd147864771b0b74901e77f2607@AcuMS.aculab.com> <20190807163629.GV2716@lahna.fi.intel.com> <91a579eb2f614739a9a1177bdde5513e@AcuMS.aculab.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <91a579eb2f614739a9a1177bdde5513e@AcuMS.aculab.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.12.1 (2019-06-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 07, 2019 at 04:41:30PM +0000, David Laight wrote: > From: 'Mika Westerberg' [mailto:mika.westerberg@linux.intel.com] > > Sent: 07 August 2019 17:36 > > > > On Wed, Aug 07, 2019 at 04:22:26PM +0000, David Laight wrote: > > > From: Mika Westerberg > > > > Sent: 07 August 2019 17:14 > > > > To: David Laight > > > > > > > > On Fri, Jul 05, 2019 at 04:04:19PM +0000, David Laight wrote: > > > > > > Really a matter of taste, but maybe you want to consider having a single > > > > > > function, with a 3rd parameter, bool is_tx. > > > > > > The calls here will be unified to: > > > > > > ring_iowrite(ring, ring->head, ring->is_tx); > > > > > > (No condition is needed here). > > > > > > > > > > > > The implementation uses the new parameter to decide which part of the register > > > > > > to mask, reducing the code duplication (in my eyes): > > > > > > > > > > > > val = ioread32(ring_desc_base(ring) + 8); > > > > > > if (is_tx) { > > > > > > val &= 0x0000ffff; > > > > > > val |= value << 16; > > > > > > } else { > > > > > > val &= 0xffff0000; > > > > > > val |= value; > > > > > > } > > > > > > iowrite32(val, ring_desc_base(ring) + 8); > > > > > > > > > > > > I'm not sure if it improves the readability or makes it worse. Your call. > > > > > > > > > > Gah, that is all horrid beyond belief. > > > > > If a 32bit write is valid then the hardware must not be updating > > > > > the other 16 bits. > > > > > In which case the driver knows what they should be. > > > > > So it can do a single 32bit write of the required value. > > > > > > > > I'm not entirely sure I understand what you say above. Can you shed some > > > > light on this by a concrete example how it should look like? :-) > > > > > > The driver must know both the tx and rx ring values, so: > > > iowrite32(tx_val << 16 | rx_val, ring_desc_base(ring) + 8); > > > > > > > I see. However, prod or cons side gets updated by the hardware as it > > processes buffers and other side is only updated by the driver. I'm not > > sure the above works here. > > If the hardware updates the other half of the 32bit word it doesn't ever work. > > In that case you must do 16bit writes. > If the hardware is ignoring the byte-enables it is broken and unusable. It is quite usable as I'm running this code on real hardware ;-) but 32-bit access is needed. The low or high 16-bits are read-only depending on the ring (Tx or Rx) and updated by the hardware. It ignores writes to that part so we could do this for Tx ring: iowrite32(prod << 16, ring_desc_base(ring) + 8); and this for Rx ring: iowrite32(cons, ring_desc_base(ring) + 8); Do you see any issues with this?