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[209.132.180.67]) by mx.google.com with ESMTP id j69si11861498plb.78.2019.08.08.07.19.19; Thu, 08 Aug 2019 07:19:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732477AbfHHMn1 (ORCPT + 99 others); Thu, 8 Aug 2019 08:43:27 -0400 Received: from esa5.microchip.iphmx.com ([216.71.150.166]:60223 "EHLO esa5.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728120AbfHHMnZ (ORCPT ); Thu, 8 Aug 2019 08:43:25 -0400 Received-SPF: Pass (esa5.microchip.iphmx.com: domain of Ludovic.Desroches@microchip.com designates 198.175.253.82 as permitted sender) identity=mailfrom; client-ip=198.175.253.82; receiver=esa5.microchip.iphmx.com; envelope-from="Ludovic.Desroches@microchip.com"; x-sender="Ludovic.Desroches@microchip.com"; x-conformance=spf_only; x-record-type="v=spf1"; x-record-text="v=spf1 mx a:ushub1.microchip.com a:smtpout.microchip.com a:mx1.microchip.iphmx.com a:mx2.microchip.iphmx.com include:servers.mcsv.net include:mktomail.com include:spf.protection.outlook.com ~all" Received-SPF: None (esa5.microchip.iphmx.com: no sender authenticity information available from domain of postmaster@email.microchip.com) identity=helo; client-ip=198.175.253.82; receiver=esa5.microchip.iphmx.com; envelope-from="Ludovic.Desroches@microchip.com"; x-sender="postmaster@email.microchip.com"; x-conformance=spf_only Authentication-Results: esa5.microchip.iphmx.com; dkim=none (message not signed) header.i=none; spf=Pass smtp.mailfrom=Ludovic.Desroches@microchip.com; spf=None smtp.helo=postmaster@email.microchip.com; dmarc=pass (p=none dis=none) d=microchip.com IronPort-SDR: 6BkT1O3KzLTrAEfzzKQKUg+ov/TLPRtRkX+Hy2eWKTrWrx6dAUCxmQ8HDSgbCnz8E6/jMTPpAL k4tC2ohBKyFmwAS4Dv1yPRX4Qt2x4vzsF53IUDGiIhgmRrf40QjlGNtNvMUJl6oTQqZM91ZeHj pdlsujUI+g2Fqo/kEdL7kNA1shBS8j2DvHBO3NqXkS6s78HEYWUrSc0WDXazgsq7L1Xu3BJoTO i4GZw3OgKZJpLmmLrAF9rD5C6Jy0sMviJ6+a8zYH2o6o8dTbU9CT1SnzA7TZm0n0fO/2IKZwaq 180= X-IronPort-AV: E=Sophos;i="5.64,361,1559545200"; d="scan'208";a="42891100" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Aug 2019 05:43:23 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 8 Aug 2019 05:43:21 -0700 Received: from localhost (10.10.85.251) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Thu, 8 Aug 2019 05:43:21 -0700 Date: Thu, 8 Aug 2019 14:42:18 +0200 From: Ludovic Desroches To: Eugen Hristev - M18282 CC: Nicolas Ferre - M43238 , "alexandre.belloni@bootlin.com" , "adrian.hunter@intel.com" , "ulf.hansson@linaro.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-mmc@vger.kernel.org" Subject: Re: [PATCH 2/2] ARM: dts: at91: sama5d27_som1_ek: add mmc capabilities for SDMMC0 Message-ID: <20190808124217.wrmcxohw5i6ju2qe@M43218.corp.atmel.com> Mail-Followup-To: Eugen Hristev - M18282 , Nicolas Ferre - M43238 , "alexandre.belloni@bootlin.com" , "adrian.hunter@intel.com" , "ulf.hansson@linaro.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-mmc@vger.kernel.org" References: <1565252928-28994-1-git-send-email-eugen.hristev@microchip.com> <1565252928-28994-2-git-send-email-eugen.hristev@microchip.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <1565252928-28994-2-git-send-email-eugen.hristev@microchip.com> User-Agent: NeoMutt/20180716 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Aug 08, 2019 at 10:35:43AM +0200, Eugen Hristev - M18282 wrote: > From: Eugen Hristev > > Add mmc capabilities for SDMMC0 for this board. > With this enabled, eMMC connected card is detected as: > > mmc0: new DDR MMC card at address 0001 > > Signed-off-by: Eugen Hristev Acked-by: Ludovic Desroches I am interested to have the some insights about the use of sd-uhs-* properties. Our IP can't deal with 1V8 by itself. It has a 1V8SEL signal which can be used as the logic control input of a mux. So even if the IP claims to support UHS modes, it depends on the board. Are the sd-uhs-* properties a way to deal with this? I tend to think no as sdhci_setup_host() will set the caps depending on the content of the capabilities register. Do we have to use the SDHCI_QUIRK_MISSING_CAPS quirk or sdhci-caps/sdhci-caps-mask? Regards Ludovic > --- > arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts > index 149e539..194b3a3 100644 > --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts > +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts > @@ -54,6 +54,7 @@ > > sdmmc0: sdio-host@a0000000 { > bus-width = <8>; > + mmc-ddr-3_3v; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_sdmmc0_default>; > status = "okay"; > -- > 2.7.4 >