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[209.132.180.67]) by mx.google.com with ESMTP id q7si3051332pjv.36.2019.08.08.16.47.45; Thu, 08 Aug 2019 16:48:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=BXlb6cQ3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404971AbfHHXrI (ORCPT + 99 others); Thu, 8 Aug 2019 19:47:08 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:12806 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2404329AbfHHXrD (ORCPT ); Thu, 8 Aug 2019 19:47:03 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 08 Aug 2019 16:47:04 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 08 Aug 2019 16:47:02 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 08 Aug 2019 16:47:02 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 8 Aug 2019 23:47:02 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 8 Aug 2019 23:47:02 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.103.110]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 08 Aug 2019 16:47:02 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v8 02/21] pinctrl: tegra: Add write barrier after all pinctrl register writes Date: Thu, 8 Aug 2019 16:46:41 -0700 Message-ID: <1565308020-31952-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1565308020-31952-1-git-send-email-skomatineni@nvidia.com> References: <1565308020-31952-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1565308024; bh=NK4pgGR6xJSTh0oyzuTnp9rDJd43CHOoKN5Ajsuwe28=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=BXlb6cQ3SBMGJQRhljRbRT60OHFwr6YmnY3ZlJHqk+8Ip9SUS8Dy5SVKJX8q7YGy9 kLBfMFMJKjsnQviM+lnapI9bzaqKzC2NVNBzDc0Ff1hhxD6Lm094OLaIzplB6s69vB djnd5ZL/UuLcCY/LS5TX1Nlyhl0fGMNtRm1VXD6eyg02hSs3xQf0SiIGFniV/UVeZE Z6VDBbb6MmPRshQ5vvZHpeQhSM+BHT5aeA6SBw5olYb8eciqOnQALDS4sbY1PuYz5p uN0M+ALfP0Zm4L/6StQwk/ELuxiX73Vp2lvmT0PCn3j49saJbSfpT9w7781J+X1OAq fFTSYV23aLL8Q== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds write barrier after all pinctrl register writes during resume to make sure all pinctrl changes are complete. Signed-off-by: Sowjanya Komatineni --- drivers/pinctrl/tegra/pinctrl-tegra.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 982ee634b3b1..f49fe29fb6df 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -677,6 +677,8 @@ static int tegra_pinctrl_resume(struct device *dev) writel_relaxed(*backup_regs++, regs++); } + /* make sure all the pinmux register writes are complete */ + wmb(); return 0; } -- 2.7.4