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Fri, 09 Aug 2019 06:13:22 -0700 (PDT) Received: from [192.168.2.145] ([94.29.34.218]) by smtp.googlemail.com with ESMTPSA id k124sm17587000lfd.60.2019.08.09.06.13.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Aug 2019 06:13:21 -0700 (PDT) Subject: Re: [PATCH v8 18/21] soc/tegra: pmc: Configure core power request polarity To: Sowjanya Komatineni , thierry.reding@gmail.com, jonathanh@nvidia.com, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, linus.walleij@linaro.org, stefan@agner.ch, mark.rutland@arm.com Cc: pdeschrijver@nvidia.com, pgaikwad@nvidia.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, jckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, mperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org, devicetree@vger.kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org, linux-pm@vger.kernel.org References: <1565308020-31952-1-git-send-email-skomatineni@nvidia.com> <1565308020-31952-19-git-send-email-skomatineni@nvidia.com> From: Dmitry Osipenko Message-ID: <29842147-a5f8-d51d-c594-b93b20b2e20f@gmail.com> Date: Fri, 9 Aug 2019 16:13:20 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.2 MIME-Version: 1.0 In-Reply-To: <1565308020-31952-19-git-send-email-skomatineni@nvidia.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 09.08.2019 2:46, Sowjanya Komatineni пишет: > This patch configures polarity of the core power request signal > in PMC control register based on the device tree property. > > PMC asserts and de-asserts power request signal based on it polarity > when it need to power-up and power-down the core rail during SC7. > > Signed-off-by: Sowjanya Komatineni > --- > drivers/soc/tegra/pmc.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c > index 3aa71c28a10a..e013ada7e4e9 100644 > --- a/drivers/soc/tegra/pmc.c > +++ b/drivers/soc/tegra/pmc.c > @@ -56,6 +56,7 @@ > #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ > #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ > #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ > +#define PMC_CNTRL_PWRREQ_POLARITY BIT(8) > #define PMC_CNTRL_MAIN_RST BIT(4) > > #define PMC_WAKE_MASK 0x0c > @@ -2290,6 +2291,11 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc) > else > value |= PMC_CNTRL_SYSCLK_POLARITY; > > + if (pmc->corereq_high) > + value &= ~PMC_CNTRL_PWRREQ_POLARITY; > + else > + value |= PMC_CNTRL_PWRREQ_POLARITY; > + > /* configure the output polarity while the request is tristated */ > tegra_pmc_writel(pmc, value, PMC_CNTRL); > > Reviewed-by: Dmitry Osipenko