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Message-ID: <cb8a7d13a31588205d1c18521e58a0ee4bac03f8.camel@linux.intel.com>
Subject: Re: [PATCH v21 16/28] x86/sgx: Add the Linux SGX Enclave Driver
From:   Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
To:     Sean Christopherson <sean.j.christopherson@intel.com>
Cc:     "Ayoun, Serge" <serge.ayoun@intel.com>,
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        "Hansen, Dave" <dave.hansen@intel.com>,
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        "npmccallum@redhat.com" <npmccallum@redhat.com>,
        "Katz-zamir, Shay" <shay.katz-zamir@intel.com>,
        "Huang, Haitao" <haitao.huang@intel.com>,
        "andriy.shevchenko@linux.intel.com" 
        <andriy.shevchenko@linux.intel.com>,
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        "Xing, Cedric" <cedric.xing@intel.com>
Date:   Fri, 09 Aug 2019 18:02:08 +0300
In-Reply-To: <20190808154000.GB23156@linux.intel.com>
References: <20190713170804.2340-1-jarkko.sakkinen@linux.intel.com>
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         <20190807151534.kxsletvhbn3lno6w@linux.intel.com>
         <20190808154000.GB23156@linux.intel.com>
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On Thu, 2019-08-08 at 08:40 -0700, Sean Christopherson wrote:
> On Wed, Aug 07, 2019 at 06:15:34PM +0300, Jarkko Sakkinen wrote:
> > On Mon, Jul 29, 2019 at 11:17:57AM +0000, Ayoun, Serge wrote:
> > > > +	/* TCS pages need to be RW in the PTEs, but can be 0 in the EPCM. */
> > > > +	if ((secinfo.flags & SGX_SECINFO_PAGE_TYPE_MASK) ==
> > > > SGX_SECINFO_TCS)
> > > > +		prot |= PROT_READ | PROT_WRITE;
> > > 
> > > For TCS pages you add both RD and WR maximum protection bits.
> > > For the enclave to be able to run, user mode will have to change the
> > > "vma->vm_flags" from PROT_NONE to PROT_READ | PROT_WRITE (otherwise
> > > eenter fails).  This is exactly what your selftest  does.
> > 
> > Recap where the TCS requirements came from? Why does it need
> > RW in PTEs and can be 0 in the EPCM? The comment should explain
> > it rather leave it as a claim IMHO.
> 
> Hardware ignores SECINFO.FLAGS.{R,W,X} coming from userspace and instead
> forces RWX=0.  It does this to prevent software from directly accessing
> the TCS.  But hardware still accesses the TCS through a virtual address,
> e.g. to allow software to zap the page for reclaim, which means hardware
> generates reads and writes to the TCS, i.e. the PTEs need RW permissions.

Manipulating a PTE should not require any specific permissions on the
page that it is defining. Why RW is required in SGX context?

> So, for the EADD ioctl(), it's not unreasonable for userspace to provide
> SECINFO.FLAGS.{R,W,X} = 0 for the TCS to match what will actually get
> jammed into the EPCM.  Allowing userspace to specify RWX=0 means the
> kernel needs to manually add PROT_READ and PROT_WRITE to the allowed prot
> bits so that mmap()/mprotect() work as expected.

Anyway, appreciate your throughtout explanation, thanks.

/Jarkko