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From:   Dan Williams <dan.j.williams@intel.com>
Date:   Sat, 10 Aug 2019 13:22:12 -0700
Message-ID: <CAA9_cmcm_0tzBLQeEH7KsZxK4fggfSu2zDYRieajtoYS5ZidBA@mail.gmail.com>
Subject: Re: [PATCH] ata: ahci: Lookup PCS register offset based on PCI device ID
To:     Christoph Hellwig <hch@infradead.org>
Cc:     Stephen Douthit <stephend@silicom-usa.com>,
        Jens Axboe <axboe@kernel.dk>,
        "linux-ide@vger.kernel.org" <linux-ide@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
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On Sat, Aug 10, 2019 at 12:43 AM Christoph Hellwig <hch@infradead.org> wrote:
>
> On Thu, Aug 08, 2019 at 08:24:31PM +0000, Stephen Douthit wrote:
> > Intel moved the PCS register from 0x92 to 0x94 on Denverton for some
> > reason, so now we get to check the device ID before poking it on reset.
>
> And now you just match on the new IDs, which means we'll perpetually
> catch up on any new device.  Dan, can you reach out inside Intel to
> figure out if there is a way to find out the PCS register location
> without the PCI ID check?

I'll ask. One guess for now is that num_ports >= 8 indicates the new
layout since the old layout ran out of space, but that might fall over
if the SOC uses the new layout, but implements fewer ports.