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From:   "james qian wang (Arm Technology China)" <james.qian.wang@arm.com>
To:     "Gustavo A. R. Silva" <gustavo@embeddedor.com>
CC:     Liviu Dudau <Liviu.Dudau@arm.com>,
        Brian Starkey <Brian.Starkey@arm.com>,
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        "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>,
        nd <nd@arm.com>
Subject: Re: drm/komeda: Fix potential integer overflow in
 komeda_crtc_update_clock_ratio
Thread-Topic: drm/komeda: Fix potential integer overflow in
 komeda_crtc_update_clock_ratio
Thread-Index: AQHVUPc+rOyABKz0zU+Ka9N6ADVAww==
Date:   Mon, 12 Aug 2019 10:18:11 +0000
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On Sun, Aug 11, 2019 at 07:08:01PM -0500, Gustavo A. R. Silva wrote:
> Add suffix ULL to constant 1000 in order to avoid a potential integer
> overflow and give the compiler complete information about the proper
> arithmetic to use. Notice that this constant is being used in a context
> that expects an expression of type u64, but it's currently evaluated
> using 32-bit arithmetic.
>=20
> Addresses-Coverity-ID: 1485796 ("Unintentional integer overflow")
> Fixes: ed22c6d9304d ("drm/komeda: Use drm_display_mode "crtc_" prefixed h=
ardware timings")
> Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
> ---
>  drivers/gpu/drm/arm/display/komeda/komeda_crtc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>=20
> diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/g=
pu/drm/arm/display/komeda/komeda_crtc.c
> index fa9a4593bb37..624d257da20f 100644
> --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
> +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
> @@ -27,7 +27,7 @@ static void komeda_crtc_update_clock_ratio(struct komed=
a_crtc_state *kcrtc_st)
>  		return;
>  	}
> =20
> -	pxlclk =3D kcrtc_st->base.adjusted_mode.crtc_clock * 1000;
> +	pxlclk =3D kcrtc_st->base.adjusted_mode.crtc_clock * 1000ULL;
>  	aclk =3D komeda_crtc_get_aclk(kcrtc_st);
> =20
>  	kcrtc_st->clock_ratio =3D div64_u64(aclk << 32, pxlclk);

Thank you for the patch.

Reviewed-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.co=
m>