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[209.132.180.67]) by mx.google.com with ESMTP id h30si8500980pjb.45.2019.08.12.03.46.21; Mon, 12 Aug 2019 03:46:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727917AbfHLKpc (ORCPT + 99 others); Mon, 12 Aug 2019 06:45:32 -0400 Received: from foss.arm.com ([217.140.110.172]:48106 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727691AbfHLKpc (ORCPT ); Mon, 12 Aug 2019 06:45:32 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1BA0715AB; Mon, 12 Aug 2019 03:45:31 -0700 (PDT) Received: from dawn-kernel.cambridge.arm.com (unknown [10.1.197.116]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 677F73F706; Mon, 12 Aug 2019 03:45:30 -0700 (PDT) Subject: Re: [PATCH] coresight: tmc-etr: Fix perf_data check. To: yabinc@google.com, mathieu.poirier@linaro.org, alexander.shishkin@linux.intel.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20190809202330.51183-1-yabinc@google.com> From: Suzuki K Poulose Message-ID: <8b154f20-60d9-74a4-8e5d-65ad612dc387@arm.com> Date: Mon, 12 Aug 2019 11:45:29 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190809202330.51183-1-yabinc@google.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 09/08/2019 21:23, Yabin Cui wrote: > When tracing etm data of multiple threads on multiple cpus through > perf interface, each cpu has a unique etr_perf_buffer while sharing > the same etr device. There is no guarantee that the last cpu starts > etm tracing also stops last. This makes perf_data check fail. > > Fix it by checking etr_buf instead of etr_perf_buffer. Please could you add a Fixes tag for this: Fixes: 3147da92a8a81fc3 ("coresight: tmc-etr: Allocate and free ETR memory buffers for CPU-wide scenarios") as the problem was introduced as a side effect of the above patch ? > > Signed-off-by: Yabin Cui > --- > drivers/hwtracing/coresight/coresight-tmc-etr.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c > index 17006705287a..f466f05afe08 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c > @@ -1484,7 +1484,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev, > goto out; > } > > - if (WARN_ON(drvdata->perf_data != etr_perf)) { > + if (WARN_ON(drvdata->perf_data != etr_buf)) { > lost = true; > spin_unlock_irqrestore(&drvdata->spinlock, flags); > goto out; > @@ -1556,7 +1556,7 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data) > } > > etr_perf->head = PERF_IDX2OFF(handle->head, etr_perf); > - drvdata->perf_data = etr_perf; > + drvdata->perf_data = etr_perf->etr_buf; minor nit: Now that we are storing the etr_buf instead of the etr_perf_buf in perf_data, we could make the "perf_data" => "perf_buf" inline with the sysfs_buf. Either ways: Reviewed-by: Suzuki K Poulose