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From:   "james qian wang (Arm Technology China)" <james.qian.wang@arm.com>
To:     "Lowry Li (Arm Technology China)" <Lowry.Li@arm.com>
CC:     Liviu Dudau <Liviu.Dudau@arm.com>,
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Subject: Re: drm/komeda: Adds internal bpp computing for arm afbc only format
 YU08 YU10
Thread-Topic: drm/komeda: Adds internal bpp computing for arm afbc only format
 YU08 YU10
Thread-Index: AQHVUPwa45rlrHJFJkaIagZP40lFIw==
Date:   Mon, 12 Aug 2019 10:52:59 +0000
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On Tue, Aug 06, 2019 at 06:31:56AM +0000, Lowry Li (Arm Technology China) w=
rote:
> From: "Lowry Li (Arm Technology China)" <Lowry.Li@arm.com>
>=20
> The drm_format_info doesn't have any cpp or block_size (both are zero)
> information for arm only afbc format YU08/YU10. we need to compute it
> by ourselves.
>=20
> Changes since v1:
> 1. Removed redundant warning check in komeda_get_afbc_format_bpp();
> 2. Removed a redundant empty line;
> 3. Rebased the branch.
>=20
> Signed-off-by: Lowry Li (Arm Technology China) <lowry.li@arm.com>
> ---
>  .../gpu/drm/arm/display/komeda/komeda_format_caps.c   | 19 +++++++++++++=
++++++
>  .../gpu/drm/arm/display/komeda/komeda_format_caps.h   |  3 +++
>  .../gpu/drm/arm/display/komeda/komeda_framebuffer.c   |  5 +++--
>  3 files changed, 25 insertions(+), 2 deletions(-)
>=20
> diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_format_caps.c b/dr=
ivers/gpu/drm/arm/display/komeda/komeda_format_caps.c
> index cd4d9f5..c9a1edb 100644
> --- a/drivers/gpu/drm/arm/display/komeda/komeda_format_caps.c
> +++ b/drivers/gpu/drm/arm/display/komeda/komeda_format_caps.c
> @@ -35,6 +35,25 @@
>  	return NULL;
>  }
> =20
> +u32 komeda_get_afbc_format_bpp(const struct drm_format_info *info, u64 m=
odifier)
> +{
> +	u32 bpp;
> +
> +	switch (info->format) {
> +	case DRM_FORMAT_YUV420_8BIT:
> +		bpp =3D 12;
> +		break;
> +	case DRM_FORMAT_YUV420_10BIT:
> +		bpp =3D 15;
> +		break;
> +	default:
> +		bpp =3D info->cpp[0] * 8;
> +		break;
> +	}
> +
> +	return bpp;
> +}
> +
>  /* Two assumptions
>   * 1. RGB always has YTR
>   * 2. Tiled RGB always has SC
> diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_format_caps.h b/dr=
ivers/gpu/drm/arm/display/komeda/komeda_format_caps.h
> index 3631910..32273cf 100644
> --- a/drivers/gpu/drm/arm/display/komeda/komeda_format_caps.h
> +++ b/drivers/gpu/drm/arm/display/komeda/komeda_format_caps.h
> @@ -97,6 +97,9 @@ static inline const char *komeda_get_format_name(u32 fo=
urcc, u64 modifier)
>  komeda_get_format_caps(struct komeda_format_caps_table *table,
>  		       u32 fourcc, u64 modifier);
> =20
> +u32 komeda_get_afbc_format_bpp(const struct drm_format_info *info,
> +			       u64 modifier);
> +
>  u32 *komeda_get_layer_fourcc_list(struct komeda_format_caps_table *table=
,
>  				  u32 layer_type, u32 *n_fmts);
> =20
> diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c b/dr=
ivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c
> index 3b0a70e..1b01a62 100644
> --- a/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c
> +++ b/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c
> @@ -43,7 +43,7 @@ static int komeda_fb_create_handle(struct drm_framebuff=
er *fb,
>  	struct drm_framebuffer *fb =3D &kfb->base;
>  	const struct drm_format_info *info =3D fb->format;
>  	struct drm_gem_object *obj;
> -	u32 alignment_w =3D 0, alignment_h =3D 0, alignment_header, n_blocks;
> +	u32 alignment_w =3D 0, alignment_h =3D 0, alignment_header, n_blocks, b=
pp;
>  	u64 min_size;
> =20
>  	obj =3D drm_gem_object_lookup(file, mode_cmd->handles[0]);
> @@ -88,8 +88,9 @@ static int komeda_fb_create_handle(struct drm_framebuff=
er *fb,
>  	kfb->offset_payload =3D ALIGN(n_blocks * AFBC_HEADER_SIZE,
>  				    alignment_header);
> =20
> +	bpp =3D komeda_get_afbc_format_bpp(info, fb->modifier);
>  	kfb->afbc_size =3D kfb->offset_payload + n_blocks *
> -			 ALIGN(info->cpp[0] * AFBC_SUPERBLK_PIXELS,
> +			 ALIGN(bpp * AFBC_SUPERBLK_PIXELS / 8,
>  			       AFBC_SUPERBLK_ALIGNMENT);
>  	min_size =3D kfb->afbc_size + fb->offsets[0];
>  	if (min_size > obj->size) {

Looks good to me.

Reviewed-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.co=
m>