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To: Xiaowei Bao , , , , , , , , , , , , , , , , , References: <20190813025317.48290-1-xiaowei.bao@nxp.com> From: Kishon Vijay Abraham I Message-ID: <4a456d72-f5b5-e860-0215-dd215e2edf09@ti.com> Date: Tue, 13 Aug 2019 10:06:20 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190813025317.48290-1-xiaowei.bao@nxp.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 13/08/19 8:23 AM, Xiaowei Bao wrote: > The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1 > is 32bit, BAR3 and BAR4 is 64bit, this is determined by hardware, Do you mean BAR2 instead of BAR3 here? Thanks Kishon > so set the bar_fixed_64bit with 0x14. > > Signed-off-by: Xiaowei Bao > --- > v2: > - Replace value 0x14 with a macro. > v3: > - No change. > v4: > - send the patch again with '--to'. > > drivers/pci/controller/dwc/pci-layerscape-ep.c | 1 + > 1 files changed, 1 insertions(+), 0 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c > index be61d96..227c33b 100644 > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c > @@ -44,6 +44,7 @@ static int ls_pcie_establish_link(struct dw_pcie *pci) > .linkup_notifier = false, > .msi_capable = true, > .msix_capable = false, > + .bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4), > }; > > static const struct pci_epc_features* >